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1 parent 5785636 commit 96e8828Copy full SHA for 96e8828
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2287,8 +2287,9 @@ bool RISCVInstrInfo::shouldClusterMemOps(
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// Assume a cache line size of 64 bytes if no size is set in RISCVSubtarget.
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CacheLineSize = CacheLineSize ? CacheLineSize : 64;
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// Cluster if the memory operations are on the same or a neighbouring cache
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- // line.
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- return std::abs(Offset1 - Offset2) < CacheLineSize;
+ // line, but limit the maximum ClusterSize to avoid creating too much
+ // additional register pressure.
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+ return ClusterSize <= 4 && std::abs(Offset1 - Offset2) < CacheLineSize;
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}
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// Set BaseReg (the base register operand), Offset (the byte offset being
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