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[MC] Store target Insts table in reverse order. NFC.
This will allow an entry in the table to access data that is stored immediately after the end of the table, by adding its opcode value to its address. Differential Revision: https://reviews.llvm.org/D142217
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3 files changed

+10
-9
lines changed

3 files changed

+10
-9
lines changed

llvm/include/llvm/MC/MCInstrInfo.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ class MCInstrInfo {
3030
std::string &);
3131

3232
private:
33-
const MCInstrDesc *Desc; // Raw array to allow static init'n
33+
const MCInstrDesc *LastDesc; // Raw array to allow static init'n
3434
const unsigned *InstrNameIndices; // Array for name indices in InstrNameData
3535
const char *InstrNameData; // Instruction name string pool
3636
// Subtarget feature that an instruction is deprecated on, if any
@@ -48,7 +48,7 @@ class MCInstrInfo {
4848
void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND,
4949
const uint8_t *DF,
5050
const ComplexDeprecationPredicate *CDI, unsigned NO) {
51-
Desc = D;
51+
LastDesc = D + NO - 1;
5252
InstrNameIndices = NI;
5353
InstrNameData = ND;
5454
DeprecatedFeatures = DF;
@@ -62,7 +62,8 @@ class MCInstrInfo {
6262
/// specified instruction opcode.
6363
const MCInstrDesc &get(unsigned Opcode) const {
6464
assert(Opcode < NumOpcodes && "Invalid opcode!");
65-
return Desc[Opcode];
65+
// The table is indexed backwards from the last entry.
66+
return *(LastDesc - Opcode);
6667
}
6768

6869
/// Returns the name for the instructions with the given opcode.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2503,7 +2503,8 @@ class ARMOperand : public MCParsedAsmOperand {
25032503
RegNum = 0;
25042504
} else {
25052505
unsigned NextOpIndex = Inst.getNumOperands();
2506-
const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
2506+
const MCInstrDesc &MCID =
2507+
ARMInsts[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()];
25072508
int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
25082509
assert(TiedOp >= 0 &&
25092510
"Inactive register in vpred_r is not tied to an output!");

llvm/utils/TableGen/InstrInfoEmitter.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -924,20 +924,19 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
924924
Records.startTimer("Emit operand info");
925925
EmitOperandInfo(OS, OperandInfoIDs);
926926

927-
// Emit all of the MCInstrDesc records in their ENUM ordering.
928-
//
927+
// Emit all of the MCInstrDesc records in reverse ENUM ordering.
929928
Records.startTimer("Emit InstrDesc records");
930929
OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
931930
ArrayRef<const CodeGenInstruction*> NumberedInstructions =
932931
Target.getInstructionsByEnumValue();
933932

934933
SequenceToOffsetTable<std::string> InstrNames;
935-
unsigned Num = 0;
936-
for (const CodeGenInstruction *Inst : NumberedInstructions) {
934+
unsigned Num = NumberedInstructions.size();
935+
for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) {
937936
// Keep a list of the instruction names.
938937
InstrNames.add(std::string(Inst->TheDef->getName()));
939938
// Emit the record into the table.
940-
emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
939+
emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoIDs, OS);
941940
}
942941
OS << "};\n\n";
943942

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