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‎llvm/test/CodeGen/AArch64/neon-mla-mls.ll

Lines changed: 61 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,85 +1,134 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
23

34

45
define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
5-
;CHECK: mla {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
6+
; CHECK-LABEL: mla8xi8:
7+
; CHECK: // %bb.0:
8+
; CHECK-NEXT: mla v2.8b, v0.8b, v1.8b
9+
; CHECK-NEXT: mov v0.16b, v2.16b
10+
; CHECK-NEXT: ret
611
%tmp1 = mul <8 x i8> %A, %B;
712
%tmp2 = add <8 x i8> %C, %tmp1;
813
ret <8 x i8> %tmp2
914
}
1015

1116
define <16 x i8> @mla16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
12-
;CHECK: mla {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
17+
; CHECK-LABEL: mla16xi8:
18+
; CHECK: // %bb.0:
19+
; CHECK-NEXT: mla v2.16b, v0.16b, v1.16b
20+
; CHECK-NEXT: mov v0.16b, v2.16b
21+
; CHECK-NEXT: ret
1322
%tmp1 = mul <16 x i8> %A, %B;
1423
%tmp2 = add <16 x i8> %C, %tmp1;
1524
ret <16 x i8> %tmp2
1625
}
1726

1827
define <4 x i16> @mla4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
19-
;CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
28+
; CHECK-LABEL: mla4xi16:
29+
; CHECK: // %bb.0:
30+
; CHECK-NEXT: mla v2.4h, v0.4h, v1.4h
31+
; CHECK-NEXT: mov v0.16b, v2.16b
32+
; CHECK-NEXT: ret
2033
%tmp1 = mul <4 x i16> %A, %B;
2134
%tmp2 = add <4 x i16> %C, %tmp1;
2235
ret <4 x i16> %tmp2
2336
}
2437

2538
define <8 x i16> @mla8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
26-
;CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
39+
; CHECK-LABEL: mla8xi16:
40+
; CHECK: // %bb.0:
41+
; CHECK-NEXT: mla v2.8h, v0.8h, v1.8h
42+
; CHECK-NEXT: mov v0.16b, v2.16b
43+
; CHECK-NEXT: ret
2744
%tmp1 = mul <8 x i16> %A, %B;
2845
%tmp2 = add <8 x i16> %C, %tmp1;
2946
ret <8 x i16> %tmp2
3047
}
3148

3249
define <2 x i32> @mla2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
33-
;CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
50+
; CHECK-LABEL: mla2xi32:
51+
; CHECK: // %bb.0:
52+
; CHECK-NEXT: mla v2.2s, v0.2s, v1.2s
53+
; CHECK-NEXT: mov v0.16b, v2.16b
54+
; CHECK-NEXT: ret
3455
%tmp1 = mul <2 x i32> %A, %B;
3556
%tmp2 = add <2 x i32> %C, %tmp1;
3657
ret <2 x i32> %tmp2
3758
}
3859

3960
define <4 x i32> @mla4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
40-
;CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
61+
; CHECK-LABEL: mla4xi32:
62+
; CHECK: // %bb.0:
63+
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
64+
; CHECK-NEXT: mov v0.16b, v2.16b
65+
; CHECK-NEXT: ret
4166
%tmp1 = mul <4 x i32> %A, %B;
4267
%tmp2 = add <4 x i32> %C, %tmp1;
4368
ret <4 x i32> %tmp2
4469
}
4570

4671
define <8 x i8> @mls8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
47-
;CHECK: mls {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
72+
; CHECK-LABEL: mls8xi8:
73+
; CHECK: // %bb.0:
74+
; CHECK-NEXT: mls v2.8b, v0.8b, v1.8b
75+
; CHECK-NEXT: mov v0.16b, v2.16b
76+
; CHECK-NEXT: ret
4877
%tmp1 = mul <8 x i8> %A, %B;
4978
%tmp2 = sub <8 x i8> %C, %tmp1;
5079
ret <8 x i8> %tmp2
5180
}
5281

5382
define <16 x i8> @mls16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
54-
;CHECK: mls {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
83+
; CHECK-LABEL: mls16xi8:
84+
; CHECK: // %bb.0:
85+
; CHECK-NEXT: mls v2.16b, v0.16b, v1.16b
86+
; CHECK-NEXT: mov v0.16b, v2.16b
87+
; CHECK-NEXT: ret
5588
%tmp1 = mul <16 x i8> %A, %B;
5689
%tmp2 = sub <16 x i8> %C, %tmp1;
5790
ret <16 x i8> %tmp2
5891
}
5992

6093
define <4 x i16> @mls4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
61-
;CHECK: mls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
94+
; CHECK-LABEL: mls4xi16:
95+
; CHECK: // %bb.0:
96+
; CHECK-NEXT: mls v2.4h, v0.4h, v1.4h
97+
; CHECK-NEXT: mov v0.16b, v2.16b
98+
; CHECK-NEXT: ret
6299
%tmp1 = mul <4 x i16> %A, %B;
63100
%tmp2 = sub <4 x i16> %C, %tmp1;
64101
ret <4 x i16> %tmp2
65102
}
66103

67104
define <8 x i16> @mls8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
68-
;CHECK: mls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
105+
; CHECK-LABEL: mls8xi16:
106+
; CHECK: // %bb.0:
107+
; CHECK-NEXT: mls v2.8h, v0.8h, v1.8h
108+
; CHECK-NEXT: mov v0.16b, v2.16b
109+
; CHECK-NEXT: ret
69110
%tmp1 = mul <8 x i16> %A, %B;
70111
%tmp2 = sub <8 x i16> %C, %tmp1;
71112
ret <8 x i16> %tmp2
72113
}
73114

74115
define <2 x i32> @mls2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
75-
;CHECK: mls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
116+
; CHECK-LABEL: mls2xi32:
117+
; CHECK: // %bb.0:
118+
; CHECK-NEXT: mls v2.2s, v0.2s, v1.2s
119+
; CHECK-NEXT: mov v0.16b, v2.16b
120+
; CHECK-NEXT: ret
76121
%tmp1 = mul <2 x i32> %A, %B;
77122
%tmp2 = sub <2 x i32> %C, %tmp1;
78123
ret <2 x i32> %tmp2
79124
}
80125

81126
define <4 x i32> @mls4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
82-
;CHECK: mls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
127+
; CHECK-LABEL: mls4xi32:
128+
; CHECK: // %bb.0:
129+
; CHECK-NEXT: mls v2.4s, v0.4s, v1.4s
130+
; CHECK-NEXT: mov v0.16b, v2.16b
131+
; CHECK-NEXT: ret
83132
%tmp1 = mul <4 x i32> %A, %B;
84133
%tmp2 = sub <4 x i32> %C, %tmp1;
85134
ret <4 x i32> %tmp2

‎llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc %s --mtriple aarch64 -verify-machineinstrs -o - | FileCheck %s
3+
4+
define dso_local void @jsimd_idct_ifast_neon_intrinsic(i8* nocapture readonly %dct_table, i16* nocapture readonly %coef_block, i8** nocapture readonly %output_buf, i32 %output_col) local_unnamed_addr #0 {
5+
; CHECK-LABEL: jsimd_idct_ifast_neon_intrinsic:
6+
; CHECK: // %bb.0: // %entry
7+
; CHECK-NEXT: ldr q0, [x1, #32]
8+
; CHECK-NEXT: ldr q1, [x0, #32]
9+
; CHECK-NEXT: ldr q2, [x1, #96]
10+
; CHECK-NEXT: ldr q3, [x0, #96]
11+
; CHECK-NEXT: ldr x8, [x2, #48]
12+
; CHECK-NEXT: mul v0.8h, v1.8h, v0.8h
13+
; CHECK-NEXT: mov v1.16b, v0.16b
14+
; CHECK-NEXT: mla v1.8h, v3.8h, v2.8h
15+
; CHECK-NEXT: mov w9, w3
16+
; CHECK-NEXT: str q1, [x8, x9]
17+
; CHECK-NEXT: ldr x8, [x2, #56]
18+
; CHECK-NEXT: mls v0.8h, v3.8h, v2.8h
19+
; CHECK-NEXT: str q0, [x8, x9]
20+
; CHECK-NEXT: ret
21+
entry:
22+
%add.ptr5 = getelementptr inbounds i16, i16* %coef_block, i64 16
23+
%0 = bitcast i16* %add.ptr5 to <8 x i16>*
24+
%1 = load <8 x i16>, <8 x i16>* %0, align 16
25+
26+
%add.ptr17 = getelementptr inbounds i16, i16* %coef_block, i64 48
27+
%2 = bitcast i16* %add.ptr17 to <8 x i16>*
28+
%3 = load <8 x i16>, <8 x i16>* %2, align 16
29+
30+
%add.ptr29 = getelementptr inbounds i8, i8* %dct_table, i64 32
31+
%4 = bitcast i8* %add.ptr29 to <8 x i16>*
32+
%5 = load <8 x i16>, <8 x i16>* %4, align 16
33+
34+
%add.ptr41 = getelementptr inbounds i8, i8* %dct_table, i64 96
35+
%6 = bitcast i8* %add.ptr41 to <8 x i16>*
36+
%7 = load <8 x i16>, <8 x i16>* %6, align 16
37+
38+
%mul.i966 = mul <8 x i16> %5, %1
39+
%mul.i964 = mul <8 x i16> %7, %3
40+
41+
%add.i961 = add <8 x i16> %mul.i966, %mul.i964
42+
%sub.i960 = sub <8 x i16> %mul.i966, %mul.i964
43+
44+
%idx.ext = zext i32 %output_col to i64
45+
46+
%arrayidx404 = getelementptr inbounds i8*, i8** %output_buf, i64 6
47+
%8 = load i8*, i8** %arrayidx404, align 8
48+
%add.ptr406 = getelementptr inbounds i8, i8* %8, i64 %idx.ext
49+
%9 = bitcast i8* %add.ptr406 to <8 x i16>*
50+
store <8 x i16> %add.i961, <8 x i16>* %9, align 8
51+
52+
%arrayidx408 = getelementptr inbounds i8*, i8** %output_buf, i64 7
53+
%10 = load i8*, i8** %arrayidx408, align 8
54+
%add.ptr410 = getelementptr inbounds i8, i8* %10, i64 %idx.ext
55+
%11 = bitcast i8* %add.ptr410 to <8 x i16>*
56+
store <8 x i16> %sub.i960, <8 x i16>* %11, align 8
57+
58+
ret void
59+
}

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