[RISCV] Add (i32 (and GPR:, TrailingOnesMask:)) pattern for RV64 with legal i32.

Author: topperc

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2042,6 +2042,10 @@ def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
 def : PatGprImm<shl, SLLIW, uimm5, i32>;
 def : PatGprImm<srl, SRLIW, uimm5, i32>;
 def : PatGprImm<sra, SRAIW, uimm5, i32>;
+
+def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
+          (SRLI (SLLI $rs, (i64 (XLenSubTrailingOnes $mask))),
+                (i64 (XLenSubTrailingOnes $mask)))>;
 }
 
 let Predicates = [IsRV64, NotHasStdExtZba] in {

llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll

@@ -301,9 +301,8 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind {
 ;
 ; RV64IM-LABEL: udiv16_constant_lhs:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 16
-; RV64IM-NEXT:    addi a1, a1, -1
-; RV64IM-NEXT:    and a0, a0, a1
+; RV64IM-NEXT:    slli a0, a0, 48
+; RV64IM-NEXT:    srli a0, a0, 48
 ; RV64IM-NEXT:    li a1, 10
 ; RV64IM-NEXT:    divuw a0, a1, a0
 ; RV64IM-NEXT:    ret

llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll

@@ -330,9 +330,8 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
 ;
 ; RV64IM-LABEL: urem16_constant_lhs:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    lui a1, 16
-; RV64IM-NEXT:    addi a1, a1, -1
-; RV64IM-NEXT:    and a0, a0, a1
+; RV64IM-NEXT:    slli a0, a0, 48
+; RV64IM-NEXT:    srli a0, a0, 48
 ; RV64IM-NEXT:    li a1, 10
 ; RV64IM-NEXT:    remuw a0, a1, a0
 ; RV64IM-NEXT:    ret

llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll

@@ -749,9 +749,8 @@ define i64 @no_sexth_i64(i64 %a) nounwind {
 define i32 @zexth_i32(i32 %a) nounwind {
 ; RV64I-LABEL: zexth_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: zexth_i32:

llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll

@@ -944,16 +944,14 @@ define i64 @abs_i64(i64 %x) {
 define i32 @zexth_i32(i32 %a) nounwind {
 ; RV64I-LABEL: zexth_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: zexth_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    lui a1, 16
-; RV64ZBB-NEXT:    addiw a1, a1, -1
-; RV64ZBB-NEXT:    and a0, a0, a1
+; RV64ZBB-NEXT:    slli a0, a0, 48
+; RV64ZBB-NEXT:    srli a0, a0, 48
 ; RV64ZBB-NEXT:    ret
   %and = and i32 %a, 65535
   ret i32 %and

llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll

@@ -474,9 +474,8 @@ define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
 define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
 ; RV64I-LABEL: bclri_i32_31:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 524288
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 33
+; RV64I-NEXT:    srli a0, a0, 33
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bclri_i32_31: