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[AArch64] Check opcode before trying to extract register from operand
When matching FNEG patterns for the MachineCombiner we need to check for opcodes first, before trying to extract a register from an operand. Otherwise handling of instructions with non-register operands causes the compiler to crash. Differential Revision: https://reviews.llvm.org/D158473
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2 files changed

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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5514,8 +5514,8 @@ static bool getFNEGPatterns(MachineInstr &Root,
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auto Match = [&](unsigned Opcode, MachineCombinerPattern Pattern) -> bool {
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MachineOperand &MO = Root.getOperand(1);
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MachineInstr *MI = MRI.getUniqueVRegDef(MO.getReg());
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if (MI != nullptr && MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()) &&
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(MI->getOpcode() == Opcode) &&
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if (MI != nullptr && (MI->getOpcode() == Opcode) &&
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MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()) &&
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Root.getFlag(MachineInstr::MIFlag::FmContract) &&
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Root.getFlag(MachineInstr::MIFlag::FmNsz) &&
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MI->getFlag(MachineInstr::MIFlag::FmContract) &&

‎llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -mtriple aarch64 -run-pass=machine-combiner -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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@c = global double 0.000000e+00, align 8
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define void @emit_fneg_with_non_register_operand(double %c) {
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entry:
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%0 = load double, ptr @c, align 8
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%1 = tail call double asm sideeffect "", "=w,0"(double %0)
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%2 = load double, ptr @c, align 8
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%3 = tail call double asm sideeffect "", "=w,0"(double %2)
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%fneg = fneg double %1
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%cmp = fcmp oeq double %3, %fneg
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @b(double noundef %1)
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ret void
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if.end: ; preds = %entry
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ret void
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}
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declare void @b(double noundef)
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...
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---
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name: emit_fneg_with_non_register_operand
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: fpr64, preferred-register: '' }
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- { id: 1, class: fpr64, preferred-register: '' }
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- { id: 2, class: fpr64, preferred-register: '' }
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- { id: 3, class: fpr64, preferred-register: '' }
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- { id: 4, class: fpr64, preferred-register: '' }
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- { id: 5, class: fpr64, preferred-register: '' }
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- { id: 6, class: gpr64common, preferred-register: '' }
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- { id: 7, class: fpr64, preferred-register: '' }
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: true
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: emit_fneg_with_non_register_operand
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
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; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
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; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
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; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
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; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
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; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
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; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.if.then:
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; CHECK-NEXT: $d0 = COPY [[COPY]]
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; CHECK-NEXT: TCRETURNdi @b, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.if.end:
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; CHECK-NEXT: RET_ReallyLR
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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%6:gpr64common = LOADgot target-flags(aarch64-got) @c
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%3:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
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INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
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%0:fpr64 = COPY %2
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%5:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
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INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
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%7:fpr64 = FNEGDr %2
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nofpexcept FCMPDrr %4, killed %7, implicit-def $nzcv, implicit $fpcr
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Bcc 1, %bb.2, implicit $nzcv
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B %bb.1
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bb.1.if.then:
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$d0 = COPY %0
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TCRETURNdi @b, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
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bb.2.if.end:
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RET_ReallyLR
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...

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