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[RISCV] Copy typepromotion-overflow.ll from AArch64. NFC
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‎llvm/test/CodeGen/RISCV/typepromotion-overflow.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck %s
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define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: overflow_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: ori a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: srli a1, a0, 48
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; CHECK-NEXT: li a2, 1024
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; CHECK-NEXT: li a0, 2
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; CHECK-NEXT: bltu a2, a1, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: ret
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%add = add i16 %b, %a
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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define zeroext i16 @overflow_sub(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: overflow_sub:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subw a0, a0, a1
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; CHECK-NEXT: ori a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: srli a1, a0, 48
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; CHECK-NEXT: li a2, 1024
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; CHECK-NEXT: li a0, 2
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; CHECK-NEXT: bltu a2, a1, .LBB1_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: ret
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%add = sub i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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define zeroext i16 @overflow_mul(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: overflow_mul:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mul a0, a1, a0
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; CHECK-NEXT: ori a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: srli a1, a0, 48
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; CHECK-NEXT: li a2, 1024
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; CHECK-NEXT: li a0, 2
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; CHECK-NEXT: bltu a2, a1, .LBB2_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: ret
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%add = mul i16 %b, %a
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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define zeroext i16 @overflow_shl(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: overflow_shl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll a0, a0, a1
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; CHECK-NEXT: ori a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 48
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; CHECK-NEXT: srli a1, a0, 48
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; CHECK-NEXT: li a2, 1024
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; CHECK-NEXT: li a0, 2
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; CHECK-NEXT: bltu a2, a1, .LBB3_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: ret
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%add = shl i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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define i32 @overflow_add_no_consts(i8 zeroext %a, i8 zeroext %b, i8 zeroext %limit) {
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; CHECK-LABEL: overflow_add_no_consts:
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; CHECK: # %bb.0:
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: andi a1, a0, 255
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: bltu a2, a1, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: ret
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%add = add i8 %b, %a
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%cmp = icmp ugt i8 %add, %limit
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: overflow_add_const_limit:
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; CHECK: # %bb.0:
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: andi a1, a0, 255
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; CHECK-NEXT: li a2, 128
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: bltu a2, a1, .LBB5_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: ret
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%add = add i8 %b, %a
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%cmp = icmp ugt i8 %add, -128
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
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; CHECK-LABEL: overflow_add_positive_const_limit:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a0, a0, 56
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; CHECK-NEXT: srai a1, a0, 56
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; CHECK-NEXT: li a2, -1
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: blt a1, a2, .LBB6_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: ret
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%cmp = icmp slt i8 %a, -1
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @unsafe_add_underflow(i8 zeroext %a) {
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; CHECK-LABEL: unsafe_add_underflow:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: li a2, 1
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: beq a1, a2, .LBB7_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: ret
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%cmp = icmp eq i8 %a, 1
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @safe_add_underflow(i8 zeroext %a) {
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; CHECK-LABEL: safe_add_underflow:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: beqz a1, .LBB8_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB8_2:
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; CHECK-NEXT: ret
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%cmp = icmp eq i8 %a, 0
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @safe_add_underflow_neg(i8 zeroext %a) {
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; CHECK-LABEL: safe_add_underflow_neg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, a0, -2
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; CHECK-NEXT: andi a1, a0, 255
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; CHECK-NEXT: li a2, 251
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: bltu a1, a2, .LBB9_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB9_2:
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; CHECK-NEXT: ret
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%add = add i8 %a, -2
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%cmp = icmp ult i8 %add, -5
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
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; CHECK-LABEL: overflow_sub_negative_const_limit:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slli a0, a0, 56
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; CHECK-NEXT: srai a1, a0, 56
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; CHECK-NEXT: li a2, -1
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: blt a1, a2, .LBB10_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB10_2:
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; CHECK-NEXT: ret
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%cmp = icmp slt i8 %a, -1
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; This is valid so long as the icmp immediate is sext.
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define i32 @sext_sub_underflow(i8 zeroext %a) {
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; CHECK-LABEL: sext_sub_underflow:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, a0, -6
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; CHECK-NEXT: andi a1, a0, 255
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; CHECK-NEXT: li a2, 250
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: bltu a2, a1, .LBB11_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB11_2:
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; CHECK-NEXT: ret
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%sub = add i8 %a, -6
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%cmp = icmp ugt i8 %sub, -6
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @safe_sub_underflow(i8 zeroext %a) {
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; CHECK-LABEL: safe_sub_underflow:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: beqz a1, .LBB12_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: .LBB12_2:
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; CHECK-NEXT: ret
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%cmp.not = icmp eq i8 %a, 0
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%res = select i1 %cmp.not, i32 16, i32 8
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ret i32 %res
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}
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define i32 @safe_sub_underflow_neg(i8 zeroext %a) {
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; CHECK-LABEL: safe_sub_underflow_neg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, a0, -4
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; CHECK-NEXT: andi a1, a0, 255
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; CHECK-NEXT: li a2, 250
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: bltu a2, a1, .LBB13_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB13_2:
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; CHECK-NEXT: ret
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%sub = add i8 %a, -4
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%cmp = icmp ugt i8 %sub, -6
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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; This is valid so long as the icmp immediate is sext.
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define i32 @sext_sub_underflow_neg(i8 zeroext %a) {
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; CHECK-LABEL: sext_sub_underflow_neg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, a0, -4
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; CHECK-NEXT: andi a1, a0, 255
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; CHECK-NEXT: li a2, 253
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; CHECK-NEXT: li a0, 8
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; CHECK-NEXT: bltu a1, a2, .LBB14_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 16
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; CHECK-NEXT: .LBB14_2:
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; CHECK-NEXT: ret
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%sub = add i8 %a, -4
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%cmp = icmp ult i8 %sub, -3
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%res = select i1 %cmp, i32 8, i32 16
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ret i32 %res
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}
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define i32 @safe_sub_imm_var(ptr nocapture readonly %b) local_unnamed_addr #1 {
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; CHECK-LABEL: safe_sub_imm_var:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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entry:
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ret i32 0
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}
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define i32 @safe_sub_var_imm(ptr nocapture readonly %b) local_unnamed_addr #1 {
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; CHECK-LABEL: safe_sub_var_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lbu a0, 0(a0)
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; CHECK-NEXT: addi a0, a0, 8
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; CHECK-NEXT: andi a0, a0, 255
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; CHECK-NEXT: sltiu a0, a0, 253
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; CHECK-NEXT: xori a0, a0, 1
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; CHECK-NEXT: ret
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entry:
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%0 = load i8, ptr %b, align 1
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%sub = add nsw i8 %0, 8
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%cmp = icmp ugt i8 %sub, -4
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%conv4 = zext i1 %cmp to i32
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ret i32 %conv4
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}
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define i32 @safe_add_imm_var(ptr nocapture readnone %b) {
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; CHECK-LABEL: safe_add_imm_var:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: ret
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entry:
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ret i32 1
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}
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define i32 @safe_add_var_imm(ptr nocapture readnone %b) {
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; CHECK-LABEL: safe_add_var_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: ret
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entry:
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ret i32 1
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}
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define i8 @convert_add_order(i8 zeroext %arg) {
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; CHECK-LABEL: convert_add_order:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ori a1, a0, 1
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; CHECK-NEXT: sltiu a2, a1, 50
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; CHECK-NEXT: addi a1, a1, -40
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; CHECK-NEXT: andi a1, a1, 255
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; CHECK-NEXT: sltiu a1, a1, 20
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; CHECK-NEXT: li a3, 2
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; CHECK-NEXT: sub a3, a3, a1
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: or a2, a2, a3
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; CHECK-NEXT: and a0, a2, a0
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; CHECK-NEXT: ret
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%shl = or i8 %arg, 1
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%cmp.0 = icmp ult i8 %shl, 50
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%sub = add nsw i8 %shl, -40
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%cmp.1 = icmp ult i8 %sub, 20
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%mask.sel.v = select i1 %cmp.1, i8 1, i8 2
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%mask.sel = select i1 %cmp.0, i8 %mask.sel.v, i8 -1
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%res = and i8 %mask.sel, %arg
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ret i8 %res
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}
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define i8 @underflow_if_sub(i32 %arg, i8 zeroext %arg1) {
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; CHECK-LABEL: underflow_if_sub:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sext.w a2, a0
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; CHECK-NEXT: sgtz a2, a2
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; CHECK-NEXT: and a0, a2, a0
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; CHECK-NEXT: addi a0, a0, -11
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; CHECK-NEXT: andi a2, a0, 247
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; CHECK-NEXT: bltu a2, a1, .LBB20_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 100
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; CHECK-NEXT: .LBB20_2:
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; CHECK-NEXT: ret
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%cmp = icmp sgt i32 %arg, 0
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%conv = zext i1 %cmp to i32
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%and = and i32 %conv, %arg
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%trunc = trunc i32 %and to i8
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%conv1 = add nuw nsw i8 %trunc, -11
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%cmp.1 = icmp ult i8 %conv1, %arg1
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%res = select i1 %cmp.1, i8 %conv1, i8 100
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ret i8 %res
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}
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define i8 @underflow_if_sub_signext(i32 %arg, i8 signext %arg1) {
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; CHECK-LABEL: underflow_if_sub_signext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sext.w a2, a0
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; CHECK-NEXT: sgtz a2, a2
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; CHECK-NEXT: and a0, a2, a0
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; CHECK-NEXT: addi a0, a0, -11
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; CHECK-NEXT: bltu a0, a1, .LBB21_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 100
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; CHECK-NEXT: .LBB21_2:
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; CHECK-NEXT: ret
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%cmp = icmp sgt i32 %arg, 0
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%conv = zext i1 %cmp to i32
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%and = and i32 %conv, %arg
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%trunc = trunc i32 %and to i8
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%conv1 = add nuw nsw i8 %trunc, -11
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%cmp.1 = icmp ult i8 %conv1, %arg1
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%res = select i1 %cmp.1, i8 %conv1, i8 100
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ret i8 %res
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}

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