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[RISCV] Add Andes A25/AX25 processor definition
Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable CPUs that implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for A25/AX25: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25/ Scheduling model will be implemented in a later PR.
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‎clang/test/Driver/riscv-cpus.c

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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
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// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s
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// MCPU-ANDES-A25: "-target-cpu" "andes-a25"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+m"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+a"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+f"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+d"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+c"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+zbc"
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// MCPU-ANDES-A25-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s
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// MTUNE-ANDES-A25: "-tune-cpu" "andes-a25"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s
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// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+m"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+a"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+f"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+d"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+c"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbc"
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// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s
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// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
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// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
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// RISCV32-NEXT: note: valid target CPU values are:
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// RISCV32-SAME: {{^}} andes-a45
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// RISCV32-SAME: {{^}} andes-a25
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// RISCV32-SAME: {{^}}, andes-a45
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// RISCV32-SAME: {{^}}, andes-n45
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// RISCV32-SAME: {{^}}, generic-rv32
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// RISCV32-SAME: {{^}}, rocket-rv32
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are:
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// RISCV64-SAME: {{^}} andes-ax45
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// RISCV64-SAME: {{^}} andes-ax25
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// RISCV64-SAME: {{^}}, andes-ax45
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// RISCV64-SAME: {{^}}, andes-nx45
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// RISCV64-SAME: {{^}}, generic-rv64
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// RISCV64-SAME: {{^}}, mips-p8700
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are:
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// TUNE-RISCV32-SAME: {{^}} andes-a45
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// TUNE-RISCV32-SAME: {{^}} andes-a25
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// TUNE-RISCV32-SAME: {{^}}, andes-a45
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// TUNE-RISCV32-SAME: {{^}}, andes-n45
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// TUNE-RISCV32-SAME: {{^}}, generic-rv32
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// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are:
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// TUNE-RISCV64-SAME: {{^}} andes-ax45
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// TUNE-RISCV64-SAME: {{^}} andes-ax25
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// TUNE-RISCV64-SAME: {{^}}, andes-ax45
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// TUNE-RISCV64-SAME: {{^}}, andes-nx45
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// TUNE-RISCV64-SAME: {{^}}, generic-rv64
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// TUNE-RISCV64-SAME: {{^}}, mips-p8700

‎llvm/docs/ReleaseNotes.md

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* Adds assembler support for the Andes `XAndesvdot` (Andes Vector Dot Product extension).
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* Adds assembler support for the standard `Q` (Quad-Precision Floating Point)
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extension.
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* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
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FeatureStdExtZcb,
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FeatureStdExtZcmp]>;
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def ANDES_A25 : RISCVProcessorModel<"andes-a25",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbc,
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FeatureStdExtZbs]>;
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def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbc,
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FeatureStdExtZbs]>;
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def ANDES_N45 : RISCVProcessorModel<"andes-n45",
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NoSchedModel,
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[Feature32Bit,

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