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davemgreendavemgreen
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[AArch64][GlobalISel] Basic SVE and fadd
This appears to be the minimum needed to get SVE fadd working.
1 parent b5ced67 commit 9900a4d

10 files changed

+120
-58
lines changed

‎llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -277,7 +277,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
277277
}
278278

279279
const LLT Ty = MRI.getType(VReg);
280-
if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
280+
if (Ty.isValid() &&
281+
TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
281282
reportGISelFailure(
282283
MF, TPC, MORE, "gisel-select",
283284
"VReg's low-level type and register class have different sizes", *MI);

‎llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -136,8 +136,8 @@ bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
136136
unsigned Size,
137137
unsigned Offset) {
138138
unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
139-
const ValueMapping &Map =
140-
AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
139+
const ValueMapping &Map = AArch64GenRegisterBankInfo::getValueMapping(
140+
(PartialMappingIdx)FirstInBank, TypeSize::getFixed(Size))[Offset];
141141
return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
142142
Map.NumBreakDowns == 1;
143143
}
@@ -167,7 +167,7 @@ bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
167167
}
168168

169169
unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
170-
unsigned Size) {
170+
TypeSize Size) {
171171
if (RBIdx == PMI_FirstGPR) {
172172
if (Size <= 32)
173173
return 0;
@@ -178,6 +178,8 @@ unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
178178
return -1;
179179
}
180180
if (RBIdx == PMI_FirstFPR) {
181+
if (Size.isScalable())
182+
return 3;
181183
if (Size <= 16)
182184
return 0;
183185
if (Size <= 32)
@@ -197,7 +199,7 @@ unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
197199

198200
const RegisterBankInfo::ValueMapping *
199201
AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
200-
unsigned Size) {
202+
TypeSize Size) {
201203
assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
202204
unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
203205
if (BaseIdxOffset == -1u)
@@ -221,7 +223,7 @@ const AArch64GenRegisterBankInfo::PartialMappingIdx
221223

222224
const RegisterBankInfo::ValueMapping *
223225
AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
224-
unsigned SrcBankID, unsigned Size) {
226+
unsigned SrcBankID, TypeSize Size) {
225227
assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
226228
assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
227229
PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,11 @@ static cl::opt<bool> EnableExtToTBL("aarch64-enable-ext-to-tbl", cl::Hidden,
145145
static cl::opt<unsigned> MaxXors("aarch64-max-xors", cl::init(16), cl::Hidden,
146146
cl::desc("Maximum of xors"));
147147

148+
cl::opt<bool> DisableSVEGISel(
149+
"aarch64-disable-sve-gisel", cl::Hidden,
150+
cl::desc("Enable / disable SVE scalable vectors in Global ISel"),
151+
cl::init(true));
152+
148153
/// Value type used for condition codes.
149154
static const MVT MVT_CC = MVT::i32;
150155

@@ -25423,15 +25428,15 @@ bool AArch64TargetLowering::shouldLocalize(
2542325428
}
2542425429

2542525430
bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
25426-
if (Inst.getType()->isScalableTy())
25431+
if (DisableSVEGISel && Inst.getType()->isScalableTy())
2542725432
return true;
2542825433

2542925434
for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
25430-
if (Inst.getOperand(i)->getType()->isScalableTy())
25435+
if (DisableSVEGISel && Inst.getOperand(i)->getType()->isScalableTy())
2543125436
return true;
2543225437

2543325438
if (const AllocaInst *AI = dyn_cast<AllocaInst>(&Inst)) {
25434-
if (AI->getAllocatedType()->isScalableTy())
25439+
if (DisableSVEGISel && AI->getAllocatedType()->isScalableTy())
2543525440
return true;
2543625441
}
2543725442

‎llvm/lib/Target/AArch64/AArch64RegisterBanks.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>;
1414

1515
/// Floating Point/Vector Registers: B, H, S, D, Q.
16-
def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
16+
def FPRRegBank : RegisterBank<"FPR", [QQQQ, ZPR]>;
1717

1818
/// Conditional register: NZCV.
1919
def CCRegBank : RegisterBank<"CC", [CCR]>;

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@
5151

5252
using namespace llvm;
5353

54+
extern cl::opt<bool> DisableSVEGISel;
55+
5456
AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
5557
: CallLowering(&TLI) {}
5658

@@ -387,8 +389,8 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
387389
// i1 is a special case because SDAG i1 true is naturally zero extended
388390
// when widened using ANYEXT. We need to do it explicitly here.
389391
auto &Flags = CurArgInfo.Flags[0];
390-
if (MRI.getType(CurVReg).getSizeInBits() == 1 && !Flags.isSExt() &&
391-
!Flags.isZExt()) {
392+
if (MRI.getType(CurVReg).getSizeInBits() == TypeSize::getFixed(1) &&
393+
!Flags.isSExt() && !Flags.isZExt()) {
392394
CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
393395
} else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
394396
1) {
@@ -523,10 +525,10 @@ static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder,
523525

524526
bool AArch64CallLowering::fallBackToDAGISel(const MachineFunction &MF) const {
525527
auto &F = MF.getFunction();
526-
if (F.getReturnType()->isScalableTy() ||
527-
llvm::any_of(F.args(), [](const Argument &A) {
528-
return A.getType()->isScalableTy();
529-
}))
528+
if (DisableSVEGISel && (F.getReturnType()->isScalableTy() ||
529+
llvm::any_of(F.args(), [](const Argument &A) {
530+
return A.getType()->isScalableTy();
531+
})))
530532
return true;
531533
const auto &ST = MF.getSubtarget<AArch64Subtarget>();
532534
if (!ST.hasNEON() || !ST.hasFPARMv8()) {

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -595,11 +595,12 @@ getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
595595
/// Given a register bank, and size in bits, return the smallest register class
596596
/// that can represent that combination.
597597
static const TargetRegisterClass *
598-
getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits,
598+
getMinClassForRegBank(const RegisterBank &RB, TypeSize SizeInBits,
599599
bool GetAllRegSet = false) {
600600
unsigned RegBankID = RB.getID();
601601

602602
if (RegBankID == AArch64::GPRRegBankID) {
603+
assert(!SizeInBits.isScalable() && "Unexpected scalable register size");
603604
if (SizeInBits <= 32)
604605
return GetAllRegSet ? &AArch64::GPR32allRegClass
605606
: &AArch64::GPR32RegClass;
@@ -611,6 +612,12 @@ getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits,
611612
}
612613

613614
if (RegBankID == AArch64::FPRRegBankID) {
615+
if (SizeInBits.isScalable()) {
616+
assert(SizeInBits == TypeSize::getScalable(128) &&
617+
"Unexpected scalable register size");
618+
return &AArch64::ZPRRegClass;
619+
}
620+
614621
switch (SizeInBits) {
615622
default:
616623
return nullptr;
@@ -937,8 +944,8 @@ getRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII,
937944
Register SrcReg = I.getOperand(1).getReg();
938945
const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
939946
const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
940-
unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
941-
unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
947+
TypeSize DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
948+
TypeSize SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
942949

943950
// Special casing for cross-bank copies of s1s. We can technically represent
944951
// a 1-bit value with any size of register. The minimum size for a GPR is 32
@@ -948,8 +955,9 @@ getRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII,
948955
// then we can pull it into the helpers that get the appropriate class for a
949956
// register bank. Or make a new helper that carries along some constraint
950957
// information.
951-
if (SrcRegBank != DstRegBank && (DstSize == 1 && SrcSize == 1))
952-
SrcSize = DstSize = 32;
958+
if (SrcRegBank != DstRegBank &&
959+
(DstSize == TypeSize::getFixed(1) && SrcSize == TypeSize::getFixed(1)))
960+
SrcSize = DstSize = TypeSize::getFixed(32);
953961

954962
return {getMinClassForRegBank(SrcRegBank, SrcSize, true),
955963
getMinClassForRegBank(DstRegBank, DstSize, true)};
@@ -1014,10 +1022,15 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
10141022
return false;
10151023
}
10161024

1017-
unsigned SrcSize = TRI.getRegSizeInBits(*SrcRC);
1018-
unsigned DstSize = TRI.getRegSizeInBits(*DstRC);
1025+
TypeSize SrcSize = TRI.getRegSizeInBits(*SrcRC);
1026+
TypeSize DstSize = TRI.getRegSizeInBits(*DstRC);
10191027
unsigned SubReg;
10201028

1029+
if (SrcSize.isScalable()) {
1030+
assert(DstSize.isScalable() && "Unhandled scalable copy");
1031+
return true;
1032+
}
1033+
10211034
// If the source bank doesn't support a subregister copy small enough,
10221035
// then we first need to copy to the destination bank.
10231036
if (getMinSizeForRegBank(SrcRegBank) > DstSize) {

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
5959
const LLT v4s32 = LLT::fixed_vector(4, 32);
6060
const LLT v2s64 = LLT::fixed_vector(2, 64);
6161
const LLT v2p0 = LLT::fixed_vector(2, p0);
62+
const LLT nxv8s16 = LLT::scalable_vector(8, 16);
63+
const LLT nxv4s32 = LLT::scalable_vector(4, 32);
64+
const LLT nxv2s64 = LLT::scalable_vector(2, 64);
6265

6366
std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
6467
v16s8, v8s16, v4s32,
@@ -238,7 +241,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
238241
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR,
239242
G_FRINT, G_FNEARBYINT, G_INTRINSIC_TRUNC,
240243
G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
241-
.legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
244+
.legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64, nxv8s16, nxv4s32,
245+
nxv2s64})
242246
.legalIf([=](const LegalityQuery &Query) {
243247
const auto &Ty = Query.Types[0];
244248
return (Ty == v8s16 || Ty == v4s16) && HasFP16;

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 33 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -162,17 +162,18 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(
162162
unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
163163
(void)PartialMapDstIdx; \
164164
(void)PartialMapSrcIdx; \
165-
const ValueMapping *Map = getCopyMapping( \
166-
AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
165+
const ValueMapping *Map = getCopyMapping(AArch64::RBNameDst##RegBankID, \
166+
AArch64::RBNameSrc##RegBankID, \
167+
TypeSize::getFixed(Size)); \
167168
(void)Map; \
168169
assert(Map[0].BreakDown == \
169170
&AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
170-
Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
171-
" Dst is incorrectly initialized"); \
171+
Map[0].NumBreakDowns == 1 && \
172+
#RBNameDst #Size " Dst is incorrectly initialized"); \
172173
assert(Map[1].BreakDown == \
173174
&AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
174-
Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
175-
" Src is incorrectly initialized"); \
175+
Map[1].NumBreakDowns == 1 && \
176+
#RBNameSrc #Size " Src is incorrectly initialized"); \
176177
\
177178
} while (false)
178179

@@ -256,6 +257,9 @@ AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
256257
case AArch64::QQRegClassID:
257258
case AArch64::QQQRegClassID:
258259
case AArch64::QQQQRegClassID:
260+
case AArch64::ZPR_3bRegClassID:
261+
case AArch64::ZPR_4bRegClassID:
262+
case AArch64::ZPRRegClassID:
259263
return getRegBank(AArch64::FPRRegBankID);
260264
case AArch64::GPR32commonRegClassID:
261265
case AArch64::GPR32RegClassID:
@@ -300,8 +304,8 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
300304
case TargetOpcode::G_OR: {
301305
// 32 and 64-bit or can be mapped on either FPR or
302306
// GPR for the same cost.
303-
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
304-
if (Size != 32 && Size != 64)
307+
TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
308+
if (Size != TypeSize::getFixed(32) && Size != TypeSize::getFixed(64))
305309
break;
306310

307311
// If the instruction has any implicit-defs or uses,
@@ -321,8 +325,8 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
321325
return AltMappings;
322326
}
323327
case TargetOpcode::G_BITCAST: {
324-
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
325-
if (Size != 32 && Size != 64)
328+
TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
329+
if (Size != TypeSize::getFixed(32) && Size != TypeSize::getFixed(64))
326330
break;
327331

328332
// If the instruction has any implicit-defs or uses,
@@ -341,16 +345,12 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
341345
/*NumOperands*/ 2);
342346
const InstructionMapping &GPRToFPRMapping = getInstructionMapping(
343347
/*ID*/ 3,
344-
/*Cost*/
345-
copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
346-
TypeSize::getFixed(Size)),
348+
/*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
347349
getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size),
348350
/*NumOperands*/ 2);
349351
const InstructionMapping &FPRToGPRMapping = getInstructionMapping(
350352
/*ID*/ 3,
351-
/*Cost*/
352-
copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
353-
TypeSize::getFixed(Size)),
353+
/*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
354354
getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size),
355355
/*NumOperands*/ 2);
356356

@@ -361,8 +361,8 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
361361
return AltMappings;
362362
}
363363
case TargetOpcode::G_LOAD: {
364-
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
365-
if (Size != 64)
364+
TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
365+
if (Size != TypeSize::getFixed(64))
366366
break;
367367

368368
// If the instruction has any implicit-defs or uses,
@@ -373,15 +373,17 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
373373
InstructionMappings AltMappings;
374374
const InstructionMapping &GPRMapping = getInstructionMapping(
375375
/*ID*/ 1, /*Cost*/ 1,
376-
getOperandsMapping({getValueMapping(PMI_FirstGPR, Size),
377-
// Addresses are GPR 64-bit.
378-
getValueMapping(PMI_FirstGPR, 64)}),
376+
getOperandsMapping(
377+
{getValueMapping(PMI_FirstGPR, Size),
378+
// Addresses are GPR 64-bit.
379+
getValueMapping(PMI_FirstGPR, TypeSize::getFixed(64))}),
379380
/*NumOperands*/ 2);
380381
const InstructionMapping &FPRMapping = getInstructionMapping(
381382
/*ID*/ 2, /*Cost*/ 1,
382-
getOperandsMapping({getValueMapping(PMI_FirstFPR, Size),
383-
// Addresses are GPR 64-bit.
384-
getValueMapping(PMI_FirstGPR, 64)}),
383+
getOperandsMapping(
384+
{getValueMapping(PMI_FirstFPR, Size),
385+
// Addresses are GPR 64-bit.
386+
getValueMapping(PMI_FirstGPR, TypeSize::getFixed(64))}),
385387
/*NumOperands*/ 2);
386388

387389
AltMappings.push_back(&GPRMapping);
@@ -459,7 +461,7 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
459461
"This code is for instructions with 3 or less operands");
460462

461463
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
462-
unsigned Size = Ty.getSizeInBits();
464+
TypeSize Size = Ty.getSizeInBits();
463465
bool IsFPR = Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
464466

465467
PartialMappingIdx RBIdx = IsFPR ? PMI_FirstFPR : PMI_FirstGPR;
@@ -719,9 +721,9 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
719721
// If both RB are null that means both registers are generic.
720722
// We shouldn't be here.
721723
assert(DstRB && SrcRB && "Both RegBank were nullptr");
722-
unsigned Size = getSizeInBits(DstReg, MRI, TRI);
724+
TypeSize Size = getSizeInBits(DstReg, MRI, TRI);
723725
return getInstructionMapping(
724-
DefaultMappingID, copyCost(*DstRB, *SrcRB, TypeSize::getFixed(Size)),
726+
DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
725727
getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
726728
// We only care about the mapping of the destination.
727729
/*NumOperands*/ 1);
@@ -732,15 +734,15 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
732734
case TargetOpcode::G_BITCAST: {
733735
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
734736
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
735-
unsigned Size = DstTy.getSizeInBits();
737+
TypeSize Size = DstTy.getSizeInBits();
736738
bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
737739
bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
738740
const RegisterBank &DstRB =
739741
DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
740742
const RegisterBank &SrcRB =
741743
SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
742744
return getInstructionMapping(
743-
DefaultMappingID, copyCost(DstRB, SrcRB, TypeSize::getFixed(Size)),
745+
DefaultMappingID, copyCost(DstRB, SrcRB, Size),
744746
getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
745747
// We only care about the mapping of the destination for COPY.
746748
/*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
@@ -752,7 +754,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
752754
unsigned NumOperands = MI.getNumOperands();
753755

754756
// Track the size and bank of each register. We don't do partial mappings.
755-
SmallVector<unsigned, 4> OpSize(NumOperands);
757+
SmallVector<TypeSize, 4> OpSize(NumOperands, TypeSize::getFixed(0));
756758
SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
757759
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
758760
auto &MO = MI.getOperand(Idx);
@@ -833,7 +835,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
833835
Cost = copyCost(
834836
*AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank,
835837
*AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank,
836-
TypeSize::getFixed(OpSize[0]));
838+
OpSize[0]);
837839
break;
838840
case TargetOpcode::G_LOAD: {
839841
// Loading in vector unit is slightly more expensive.

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