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[X86] isAddSubOrSubAdd - convert to SDPatternMatch matching. NFC. (#144486)
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8268,6 +8268,7 @@ static bool isAddSubOrSubAdd(const BuildVectorSDNode *BV,
82688268
SDValue &Opnd0, SDValue &Opnd1,
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unsigned &NumExtracts,
82708270
bool &IsSubAdd) {
8271+
using namespace SDPatternMatch;
82718272

82728273
MVT VT = BV->getSimpleValueType(0);
82738274
if (!Subtarget.hasSSE3() || !VT.isFloatingPoint())
@@ -8302,14 +8303,8 @@ static bool isAddSubOrSubAdd(const BuildVectorSDNode *BV,
83028303
// Try to match the following pattern:
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// (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
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// Early exit if we cannot match that sequence.
8305-
if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8306-
Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8307-
!isa<ConstantSDNode>(Op0.getOperand(1)) ||
8308-
Op0.getOperand(1) != Op1.getOperand(1))
8309-
return false;
8310-
8311-
unsigned I0 = Op0.getConstantOperandVal(1);
8312-
if (I0 != i)
8306+
if (!sd_match(Op0, m_ExtractElt(m_SpecificVT(VT), m_SpecificInt(i))) ||
8307+
!sd_match(Op1, m_ExtractElt(m_SpecificVT(VT), m_SpecificInt(i))))
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return false;
83148309

83158310
// We found a valid add/sub node, make sure its the same opcode as previous
@@ -8319,16 +8314,10 @@ static bool isAddSubOrSubAdd(const BuildVectorSDNode *BV,
83198314
Opc[i % 2] = Opcode;
83208315

83218316
// Update InVec0 and InVec1.
8322-
if (InVec0.isUndef()) {
8317+
if (InVec0.isUndef())
83238318
InVec0 = Op0.getOperand(0);
8324-
if (InVec0.getSimpleValueType() != VT)
8325-
return false;
8326-
}
8327-
if (InVec1.isUndef()) {
8319+
if (InVec1.isUndef())
83288320
InVec1 = Op1.getOperand(0);
8329-
if (InVec1.getSimpleValueType() != VT)
8330-
return false;
8331-
}
83328321

83338322
// Make sure that operands in input to each add/sub node always
83348323
// come from a same pair of vectors.

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