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[SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (#91871)
This PR adds initial support for the `scmp`/`ucmp` 3-way comparison intrinsics in the SelectionDAG. Some of the expansions/lowerings are not optimal yet.
1 parent 9a86d0a commit 995835f

16 files changed

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lines changed

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

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@@ -678,6 +678,12 @@ enum NodeType {
678678
UMIN,
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UMAX,
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681+
/// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0,
682+
/// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type
683+
/// different to the result.
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SCMP,
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UCMP,
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/// Bitwise operators - logical and, logical or, logical xor.
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AND,
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OR,

‎llvm/include/llvm/CodeGen/TargetLowering.h

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@@ -5427,6 +5427,10 @@ class TargetLowering : public TargetLoweringBase {
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/// method accepts integers as its arguments.
54285428
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
54295429

5430+
/// Method for building the DAG expansion of ISD::[US]CMP. This
5431+
/// method accepts integers as its arguments
5432+
SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const;
5433+
54305434
/// Method for building the DAG expansion of ISD::[US]SHLSAT. This
54315435
/// method accepts integers as its arguments.
54325436
SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const;

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -434,6 +434,11 @@ def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
434434
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
435435
[SDNPCommutative, SDNPAssociative]>;
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437+
def scmp : SDNode<"ISD::SCMP" , SDTIntBinOp,
438+
[]>;
439+
def ucmp : SDNode<"ISD::UCMP" , SDTIntBinOp,
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[]>;
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def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
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def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
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def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1153,6 +1153,8 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
11531153
case ISD::USUBSAT:
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case ISD::SSHLSAT:
11551155
case ISD::USHLSAT:
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case ISD::SCMP:
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case ISD::UCMP:
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case ISD::FP_TO_SINT_SAT:
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case ISD::FP_TO_UINT_SAT:
11581160
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -3885,6 +3887,10 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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case ISD::USUBSAT:
38863888
Results.push_back(TLI.expandAddSubSat(Node, DAG));
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break;
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case ISD::SCMP:
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case ISD::UCMP:
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Results.push_back(TLI.expandCMP(Node, DAG));
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break;
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case ISD::SSHLSAT:
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case ISD::USHLSAT:
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Results.push_back(TLI.expandShlSat(Node, DAG));

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -236,6 +236,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
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Res = PromoteIntRes_ADDSUBSHLSAT<VPMatchContext>(N);
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break;
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case ISD::SCMP:
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case ISD::UCMP:
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Res = PromoteIntRes_CMP(N);
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break;
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case ISD::SMULFIX:
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case ISD::SMULFIXSAT:
241246
case ISD::UMULFIX:
@@ -1261,6 +1266,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
12611266
return Res;
12621267
}
12631268

1269+
SDValue DAGTypeLegalizer::PromoteIntRes_CMP(SDNode *N) {
1270+
EVT PromotedResultTy =
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TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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return DAG.getNode(N->getOpcode(), SDLoc(N), PromotedResultTy,
1273+
N->getOperand(0), N->getOperand(1));
1274+
}
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12641276
SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
12651277
SDValue Mask = N->getOperand(0);
12661278

@@ -1923,6 +1935,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
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case ISD::ROTL:
19241936
case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
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1938+
case ISD::SCMP:
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case ISD::UCMP: Res = PromoteIntOp_CMP(N); break;
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19261941
case ISD::FSHL:
19271942
case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
19281943

@@ -2233,6 +2248,17 @@ SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
22332248
ZExtPromotedInteger(N->getOperand(1))), 0);
22342249
}
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2251+
SDValue DAGTypeLegalizer::PromoteIntOp_CMP(SDNode *N) {
2252+
SDValue LHS = N->getOpcode() == ISD::UCMP
2253+
? ZExtPromotedInteger(N->getOperand(0))
2254+
: SExtPromotedInteger(N->getOperand(0));
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SDValue RHS = N->getOpcode() == ISD::UCMP
2256+
? ZExtPromotedInteger(N->getOperand(1))
2257+
: SExtPromotedInteger(N->getOperand(1));
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2259+
return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS), 0);
2260+
}
2261+
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SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
22372263
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
22382264
ZExtPromotedInteger(N->getOperand(2))), 0);
@@ -2788,6 +2814,9 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
27882814
case ISD::UMIN:
27892815
case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
27902816

2817+
case ISD::SCMP:
2818+
case ISD::UCMP: ExpandIntRes_CMP(N, Lo, Hi); break;
2819+
27912820
case ISD::ADD:
27922821
case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
27932822

@@ -3285,6 +3314,11 @@ void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
32853314
SplitInteger(Result, Lo, Hi);
32863315
}
32873316

3317+
void DAGTypeLegalizer::ExpandIntRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi) {
3318+
SDValue ExpandedCMP = TLI.expandCMP(N, DAG);
3319+
SplitInteger(ExpandedCMP, Lo, Hi);
3320+
}
3321+
32883322
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
32893323
SDValue &Lo, SDValue &Hi) {
32903324
SDLoc dl(N);
@@ -5194,6 +5228,9 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
51945228
case ISD::RETURNADDR:
51955229
case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
51965230

5231+
case ISD::SCMP:
5232+
case ISD::UCMP: Res = ExpandIntOp_CMP(N); break;
5233+
51975234
case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
51985235
case ISD::STACKMAP:
51995236
Res = ExpandIntOp_STACKMAP(N, OpNo);
@@ -5455,6 +5492,10 @@ SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
54555492
return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
54565493
}
54575494

5495+
SDValue DAGTypeLegalizer::ExpandIntOp_CMP(SDNode *N) {
5496+
return TLI.expandCMP(N, DAG);
5497+
}
5498+
54585499
SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
54595500
// The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
54605501
// surely makes pretty nice problems on 8/16 bit targets. Just truncate this

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

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Original file line numberDiff line numberDiff line change
@@ -343,6 +343,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
343343
SDValue PromoteIntRes_Overflow(SDNode *N);
344344
SDValue PromoteIntRes_FFREXP(SDNode *N);
345345
SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
346+
SDValue PromoteIntRes_CMP(SDNode *N);
346347
SDValue PromoteIntRes_Select(SDNode *N);
347348
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
348349
SDValue PromoteIntRes_SETCC(SDNode *N);
@@ -394,6 +395,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
394395
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
395396
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
396397
SDValue PromoteIntOp_Shift(SDNode *N);
398+
SDValue PromoteIntOp_CMP(SDNode *N);
397399
SDValue PromoteIntOp_FunnelShift(SDNode *N);
398400
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
399401
SDValue PromoteIntOp_VP_SIGN_EXTEND(SDNode *N);
@@ -476,6 +478,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
476478

477479
void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
478480

481+
void ExpandIntRes_CMP (SDNode *N, SDValue &Lo, SDValue &Hi);
482+
479483
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
480484
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
481485
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -505,6 +509,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
505509
SDValue ExpandIntOp_SETCC(SDNode *N);
506510
SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
507511
SDValue ExpandIntOp_Shift(SDNode *N);
512+
SDValue ExpandIntOp_CMP(SDNode *N);
508513
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
509514
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
510515
SDValue ExpandIntOp_XINT_TO_FP(SDNode *N);
@@ -805,6 +810,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
805810
void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
806811
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
807812
SDValue ScalarizeVecRes_BinOp(SDNode *N);
813+
SDValue ScalarizeVecRes_CMP(SDNode *N);
808814
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
809815
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
810816
SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
@@ -849,6 +855,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
849855
SDValue ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N);
850856
SDValue ScalarizeVecOp_VECREDUCE(SDNode *N);
851857
SDValue ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N);
858+
SDValue ScalarizeVecOp_CMP(SDNode *N);
852859

853860
//===--------------------------------------------------------------------===//
854861
// Vector Splitting Support: LegalizeVectorTypes.cpp
@@ -879,6 +886,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
879886
void SplitVectorResult(SDNode *N, unsigned ResNo);
880887
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
881888
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
889+
void SplitVecRes_CMP(SDNode *N, SDValue &Lo, SDValue &Hi);
882890
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
883891
void SplitVecRes_ADDRSPACECAST(SDNode *N, SDValue &Lo, SDValue &Hi);
884892
void SplitVecRes_FFREXP(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi);
@@ -943,6 +951,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
943951
SDValue SplitVecOp_VSETCC(SDNode *N);
944952
SDValue SplitVecOp_FP_ROUND(SDNode *N);
945953
SDValue SplitVecOp_FPOpDifferentTypes(SDNode *N);
954+
SDValue SplitVecOp_CMP(SDNode *N);
946955
SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
947956
SDValue SplitVecOp_VP_CttzElements(SDNode *N);
948957

@@ -1011,6 +1020,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
10111020

10121021
SDValue WidenVecRes_Ternary(SDNode *N);
10131022
SDValue WidenVecRes_Binary(SDNode *N);
1023+
SDValue WidenVecRes_CMP(SDNode *N);
10141024
SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
10151025
SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
10161026
SDValue WidenVecRes_StrictFP(SDNode *N);
@@ -1030,6 +1040,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
10301040
SDValue WidenVecOp_BITCAST(SDNode *N);
10311041
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
10321042
SDValue WidenVecOp_EXTEND(SDNode *N);
1043+
SDValue WidenVecOp_CMP(SDNode *N);
10331044
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
10341045
SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
10351046
SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

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Original file line numberDiff line numberDiff line change
@@ -449,6 +449,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
449449
case ISD::FP_TO_SINT_SAT:
450450
case ISD::FP_TO_UINT_SAT:
451451
case ISD::MGATHER:
452+
case ISD::SCMP:
453+
case ISD::UCMP:
452454
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
453455
break;
454456
case ISD::SMULFIX:

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