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Revert "[AArch64LoadStoreOptimizer] Generate more STPs by renaming registers earlier"
This reverts commit d96ea46, as it caused various misoptimizations, see https://reviews.llvm.org/D103597 for discussion on the issues.
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-257
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5 files changed

+48
-257
lines changed

‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Lines changed: 16 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1515,32 +1515,6 @@ static Optional<MCPhysReg> tryToFindRegisterToRename(
15151515
return None;
15161516
}
15171517

1518-
// Returns a boolean that represents whether there exists a register
1519-
// from FirstMI to the beginning of the block that can be renamed. If
1520-
// one exists, we update Flags with its value.
1521-
static bool updateFlagsWithRenameReg(
1522-
Optional<bool> MaybeCanRename, LdStPairFlags &Flags, MachineInstr &FirstMI,
1523-
MachineInstr &MI, LiveRegUnits &DefinedInBB, LiveRegUnits &UsedInBetween,
1524-
SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
1525-
const TargetRegisterInfo *TRI) {
1526-
if (DebugCounter::shouldExecute(RegRenamingCounter)) {
1527-
if (!MaybeCanRename)
1528-
MaybeCanRename = {
1529-
canRenameUpToDef(FirstMI, UsedInBetween, RequiredClasses, TRI)};
1530-
1531-
if (*MaybeCanRename) {
1532-
Optional<MCPhysReg> MaybeRenameReg = tryToFindRegisterToRename(
1533-
FirstMI, MI, DefinedInBB, UsedInBetween, RequiredClasses, TRI);
1534-
if (MaybeRenameReg) {
1535-
Flags.setRenameReg(*MaybeRenameReg);
1536-
Flags.setMergeForward(true);
1537-
return true;
1538-
}
1539-
}
1540-
}
1541-
return false;
1542-
}
1543-
15441518
/// Scan the instructions looking for a load/store that can be combined with the
15451519
/// current instruction into a wider equivalent or a load/store pair.
15461520
MachineBasicBlock::iterator
@@ -1692,27 +1666,6 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
16921666
continue;
16931667
}
16941668
}
1695-
// If the load/store pattern has been optimized and reordered
1696-
// into the following:
1697-
// ldr q0, [x1, #16]
1698-
// str q0, [x0, #16]
1699-
// ldr q0, [x1]
1700-
// str q0, [x0]
1701-
// and the destination register of the load/store instruction is
1702-
// the same register as or a sub/super register of the other
1703-
// load/store, it will not generate an LDP/STP, so we attempt to
1704-
// rename the register so that it can be recognised as a pair.
1705-
// TODO: This is currently supported for STPs, LDPs are not
1706-
// being generated yet.
1707-
if (TRI->isSuperOrSubRegisterEq(Reg, getLdStRegOp(MI).getReg())) {
1708-
bool flagsHaveRenameReg = updateFlagsWithRenameReg(
1709-
MaybeCanRename, Flags, FirstMI, MI, DefinedInBB, UsedInBetween,
1710-
RequiredClasses, TRI);
1711-
if (flagsHaveRenameReg) {
1712-
MBBIWithRenameReg = MBBI;
1713-
continue;
1714-
}
1715-
}
17161669
// If the destination register of one load is the same register or a
17171670
// sub/super register of the other load, bail and keep looking. A
17181671
// load-pair instruction with both destination registers the same is
@@ -1761,11 +1714,22 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
17611714
Flags.clearRenameReg();
17621715
return MBBI;
17631716
}
1764-
bool flagsHaveRenameReg = updateFlagsWithRenameReg(
1765-
MaybeCanRename, Flags, FirstMI, MI, DefinedInBB, UsedInBetween,
1766-
RequiredClasses, TRI);
1767-
if (flagsHaveRenameReg) {
1768-
MBBIWithRenameReg = MBBI;
1717+
1718+
if (DebugCounter::shouldExecute(RegRenamingCounter)) {
1719+
if (!MaybeCanRename)
1720+
MaybeCanRename = {canRenameUpToDef(FirstMI, UsedInBetween,
1721+
RequiredClasses, TRI)};
1722+
1723+
if (*MaybeCanRename) {
1724+
Optional<MCPhysReg> MaybeRenameReg = tryToFindRegisterToRename(
1725+
FirstMI, MI, DefinedInBB, UsedInBetween, RequiredClasses,
1726+
TRI);
1727+
if (MaybeRenameReg) {
1728+
Flags.setRenameReg(*MaybeRenameReg);
1729+
Flags.setMergeForward(true);
1730+
MBBIWithRenameReg = MBBI;
1731+
}
1732+
}
17691733
}
17701734
}
17711735
// Unable to combine these instructions due to interference in between.

‎llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll

Lines changed: 24 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -33,30 +33,38 @@ define void @call_byval_a64i32([64 x i32]* %incoming) {
3333
; CHECK-NEXT: .cfi_offset w28, -16
3434
; CHECK-NEXT: .cfi_offset w30, -24
3535
; CHECK-NEXT: .cfi_offset w29, -32
36-
; CHECK-NEXT: ldr q1, [x0]
36+
; CHECK-NEXT: ldr q0, [x0]
37+
; CHECK-NEXT: str q0, [sp]
3738
; CHECK-NEXT: ldr q0, [x0, #16]
38-
; CHECK-NEXT: stp q1, q0, [sp]
39-
; CHECK-NEXT: ldr q1, [x0, #32]
39+
; CHECK-NEXT: str q0, [sp, #16]
40+
; CHECK-NEXT: ldr q0, [x0, #32]
41+
; CHECK-NEXT: str q0, [sp, #32]
4042
; CHECK-NEXT: ldr q0, [x0, #48]
41-
; CHECK-NEXT: stp q1, q0, [sp, #32]
42-
; CHECK-NEXT: ldr q1, [x0, #64]
43+
; CHECK-NEXT: str q0, [sp, #48]
44+
; CHECK-NEXT: ldr q0, [x0, #64]
45+
; CHECK-NEXT: str q0, [sp, #64]
4346
; CHECK-NEXT: ldr q0, [x0, #80]
44-
; CHECK-NEXT: stp q1, q0, [sp, #64]
45-
; CHECK-NEXT: ldr q1, [x0, #96]
47+
; CHECK-NEXT: str q0, [sp, #80]
48+
; CHECK-NEXT: ldr q0, [x0, #96]
49+
; CHECK-NEXT: str q0, [sp, #96]
4650
; CHECK-NEXT: ldr q0, [x0, #112]
47-
; CHECK-NEXT: stp q1, q0, [sp, #96]
48-
; CHECK-NEXT: ldr q1, [x0, #128]
51+
; CHECK-NEXT: str q0, [sp, #112]
52+
; CHECK-NEXT: ldr q0, [x0, #128]
53+
; CHECK-NEXT: str q0, [sp, #128]
4954
; CHECK-NEXT: ldr q0, [x0, #144]
50-
; CHECK-NEXT: stp q1, q0, [sp, #128]
51-
; CHECK-NEXT: ldr q1, [x0, #160]
55+
; CHECK-NEXT: str q0, [sp, #144]
56+
; CHECK-NEXT: ldr q0, [x0, #160]
57+
; CHECK-NEXT: str q0, [sp, #160]
5258
; CHECK-NEXT: ldr q0, [x0, #176]
53-
; CHECK-NEXT: stp q1, q0, [sp, #160]
54-
; CHECK-NEXT: ldr q1, [x0, #192]
59+
; CHECK-NEXT: str q0, [sp, #176]
60+
; CHECK-NEXT: ldr q0, [x0, #192]
61+
; CHECK-NEXT: str q0, [sp, #192]
5562
; CHECK-NEXT: ldr q0, [x0, #208]
56-
; CHECK-NEXT: stp q1, q0, [sp, #192]
57-
; CHECK-NEXT: ldr q1, [x0, #224]
63+
; CHECK-NEXT: str q0, [sp, #208]
64+
; CHECK-NEXT: ldr q0, [x0, #224]
65+
; CHECK-NEXT: str q0, [sp, #224]
5866
; CHECK-NEXT: ldr q0, [x0, #240]
59-
; CHECK-NEXT: stp q1, q0, [sp, #224]
67+
; CHECK-NEXT: str q0, [sp, #240]
6068
; CHECK-NEXT: bl byval_a64i32
6169
; CHECK-NEXT: ldr x28, [sp, #272] // 8-byte Folded Reload
6270
; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload

‎llvm/test/CodeGen/AArch64/consthoist-gep.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@
33
; CHECK-NOT: adrp x10, global+332
44
; CHECK-NOT: add x10, x10, :lo12:global+332
55
; CHECK: adrp x10, global+528
6-
; CHECK-NEXT: and w12, w8, #0xffffff
7-
; CHECK-NEXT: ldr w8, [x11]
86
; CHECK-NEXT: add x10, x10, :lo12:global+528
97

108
%struct.blam = type { %struct.bar, %struct.bar.0, %struct.wobble, %struct.wombat, i8, i16, %struct.snork.2, %struct.foo, %struct.snork.3, %struct.wobble.4, %struct.quux, [9 x i16], %struct.spam, %struct.zot }

‎llvm/test/CodeGen/AArch64/ldst-opt.ll

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1117,7 +1117,7 @@ define void @store-pair-post-indexed-double() nounwind {
11171117
define void @post-indexed-sub-word(i32* %a, i32* %b, i64 %count) nounwind {
11181118
; CHECK-LABEL: post-indexed-sub-word
11191119
; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}], #-8
1120-
; CHECK: stp w{{[0-9]+}}, w{{[0-9]+}}, [x0, #-4]
1120+
; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}], #-8
11211121
br label %for.body
11221122
for.body:
11231123
%phi1 = phi i32* [ %gep4, %for.body ], [ %b, %0 ]
@@ -1141,7 +1141,7 @@ end:
11411141
define void @post-indexed-sub-doubleword(i64* %a, i64* %b, i64 %count) nounwind {
11421142
; CHECK-LABEL: post-indexed-sub-doubleword
11431143
; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #-16
1144-
; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0, #-8]
1144+
; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #-16
11451145
br label %for.body
11461146
for.body:
11471147
%phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ]
@@ -1165,7 +1165,7 @@ end:
11651165
define void @post-indexed-sub-quadword(<2 x i64>* %a, <2 x i64>* %b, i64 %count) nounwind {
11661166
; CHECK-LABEL: post-indexed-sub-quadword
11671167
; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}], #-32
1168-
; CHECK: stp q{{[0-9]+}}, q{{[0-9]+}}, [x0, #-16]
1168+
; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}], #-32
11691169
br label %for.body
11701170
for.body:
11711171
%phi1 = phi <2 x i64>* [ %gep4, %for.body ], [ %b, %0 ]
@@ -1189,7 +1189,7 @@ end:
11891189
define void @post-indexed-sub-float(float* %a, float* %b, i64 %count) nounwind {
11901190
; CHECK-LABEL: post-indexed-sub-float
11911191
; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}], #-8
1192-
; CHECK: stp s{{[0-9]+}}, s{{[0-9]+}}, [x0, #-4]
1192+
; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}], #-8
11931193
br label %for.body
11941194
for.body:
11951195
%phi1 = phi float* [ %gep4, %for.body ], [ %b, %0 ]
@@ -1213,7 +1213,7 @@ end:
12131213
define void @post-indexed-sub-double(double* %a, double* %b, i64 %count) nounwind {
12141214
; CHECK-LABEL: post-indexed-sub-double
12151215
; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}], #-16
1216-
; CHECK: stp d{{[0-9]+}}, d{{[0-9]+}}, [x0, #-8]
1216+
; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}], #-16
12171217
br label %for.body
12181218
for.body:
12191219
%phi1 = phi double* [ %gep4, %for.body ], [ %b, %0 ]
@@ -1237,7 +1237,7 @@ end:
12371237
define void @post-indexed-sub-doubleword-offset-min(i64* %a, i64* %b, i64 %count) nounwind {
12381238
; CHECK-LABEL: post-indexed-sub-doubleword-offset-min
12391239
; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #-256
1240-
; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0], #-256
1240+
; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #-256
12411241
br label %for.body
12421242
for.body:
12431243
%phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ]
@@ -1262,7 +1262,8 @@ define void @post-indexed-doubleword-offset-out-of-range(i64* %a, i64* %b, i64 %
12621262
; CHECK-LABEL: post-indexed-doubleword-offset-out-of-range
12631263
; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}]
12641264
; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #256
1265-
; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x0], #256
1265+
; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}]
1266+
; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #256
12661267

12671268
br label %for.body
12681269
for.body:

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