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[Alignment][NFC] Deprecate MachineMemOperand::getMachineMemOperand version that takes an untyped alignement.
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77138
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-99
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5 files changed

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‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -819,12 +819,15 @@ class MachineFunction {
819819
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
820820

821821
/// FIXME: Remove once transition to Align is over.
822-
inline MachineMemOperand *getMachineMemOperand(
823-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s,
824-
unsigned base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
825-
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
826-
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
827-
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
822+
LLVM_ATTRIBUTE_DEPRECATED(
823+
inline MachineMemOperand *getMachineMemOperand(
824+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s,
825+
unsigned base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
826+
const MDNode *Ranges = nullptr,
827+
SyncScope::ID SSID = SyncScope::System,
828+
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
829+
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic),
830+
"Use the version that takes Align instead") {
828831
return getMachineMemOperand(PtrInfo, f, s, Align(base_alignment), AAInfo,
829832
Ranges, SSID, Ordering, FailureOrdering);
830833
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6679,19 +6679,17 @@ SDValue SelectionDAG::getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl) {
66796679

66806680
SDValue SelectionDAG::getMemIntrinsicNode(
66816681
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
6682-
EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align,
6682+
EVT MemVT, MachinePointerInfo PtrInfo, unsigned Alignment,
66836683
MachineMemOperand::Flags Flags, uint64_t Size, const AAMDNodes &AAInfo) {
6684-
if (Align == 0) // Ensure that codegen never sees alignment 0
6685-
Align = getEVTAlignment(MemVT);
6686-
66876684
if (!Size && MemVT.isScalableVector())
66886685
Size = MemoryLocation::UnknownSize;
66896686
else if (!Size)
66906687
Size = MemVT.getStoreSize();
66916688

66926689
MachineFunction &MF = getMachineFunction();
6693-
MachineMemOperand *MMO =
6694-
MF.getMachineMemOperand(PtrInfo, Flags, Size, Align, AAInfo);
6690+
MachineMemOperand *MMO = MF.getMachineMemOperand(
6691+
PtrInfo, Flags, Size, Alignment ? Align(Alignment) : getEVTAlign(MemVT),
6692+
AAInfo);
66956693

66966694
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, MMO);
66976695
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 49 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -4173,25 +4173,26 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
41734173
bool IsCompressing) {
41744174
SDLoc sdl = getCurSDLoc();
41754175

4176-
auto getMaskedStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4177-
unsigned& Alignment) {
4176+
auto getMaskedStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4177+
MaybeAlign &Alignment) {
41784178
// llvm.masked.store.*(Src0, Ptr, alignment, Mask)
41794179
Src0 = I.getArgOperand(0);
41804180
Ptr = I.getArgOperand(1);
4181-
Alignment = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
4181+
Alignment =
4182+
MaybeAlign(cast<ConstantInt>(I.getArgOperand(2))->getZExtValue());
41824183
Mask = I.getArgOperand(3);
41834184
};
4184-
auto getCompressingStoreOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4185-
unsigned& Alignment) {
4185+
auto getCompressingStoreOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4186+
MaybeAlign &Alignment) {
41864187
// llvm.masked.compressstore.*(Src0, Ptr, Mask)
41874188
Src0 = I.getArgOperand(0);
41884189
Ptr = I.getArgOperand(1);
41894190
Mask = I.getArgOperand(2);
4190-
Alignment = 0;
4191+
Alignment = None;
41914192
};
41924193

41934194
Value *PtrOperand, *MaskOperand, *Src0Operand;
4194-
unsigned Alignment;
4195+
MaybeAlign Alignment;
41954196
if (IsCompressing)
41964197
getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
41974198
else
@@ -4204,19 +4205,16 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
42044205

42054206
EVT VT = Src0.getValueType();
42064207
if (!Alignment)
4207-
Alignment = DAG.getEVTAlignment(VT);
4208+
Alignment = DAG.getEVTAlign(VT);
42084209

42094210
AAMDNodes AAInfo;
42104211
I.getAAMetadata(AAInfo);
42114212

4212-
MachineMemOperand *MMO =
4213-
DAG.getMachineFunction().
4214-
getMachineMemOperand(MachinePointerInfo(PtrOperand),
4215-
MachineMemOperand::MOStore,
4216-
// TODO: Make MachineMemOperands aware of scalable
4217-
// vectors.
4218-
VT.getStoreSize().getKnownMinSize(),
4219-
Alignment, AAInfo);
4213+
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4214+
MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore,
4215+
// TODO: Make MachineMemOperands aware of scalable
4216+
// vectors.
4217+
VT.getStoreSize().getKnownMinSize(), *Alignment, AAInfo);
42204218
SDValue StoreNode =
42214219
DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO,
42224220
ISD::UNINDEXED, false /* Truncating */, IsCompressing);
@@ -4316,9 +4314,9 @@ void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
43164314
SDValue Src0 = getValue(I.getArgOperand(0));
43174315
SDValue Mask = getValue(I.getArgOperand(3));
43184316
EVT VT = Src0.getValueType();
4319-
unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
4317+
MaybeAlign Alignment(cast<ConstantInt>(I.getArgOperand(2))->getZExtValue());
43204318
if (!Alignment)
4321-
Alignment = DAG.getEVTAlignment(VT);
4319+
Alignment = DAG.getEVTAlign(VT);
43224320
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
43234321

43244322
AAMDNodes AAInfo;
@@ -4331,13 +4329,11 @@ void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
43314329
bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this);
43324330

43334331
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
4334-
MachineMemOperand *MMO = DAG.getMachineFunction().
4335-
getMachineMemOperand(MachinePointerInfo(AS),
4336-
MachineMemOperand::MOStore,
4337-
// TODO: Make MachineMemOperands aware of scalable
4338-
// vectors.
4339-
MemoryLocation::UnknownSize,
4340-
Alignment, AAInfo);
4332+
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4333+
MachinePointerInfo(AS), MachineMemOperand::MOStore,
4334+
// TODO: Make MachineMemOperands aware of scalable
4335+
// vectors.
4336+
MemoryLocation::UnknownSize, *Alignment, AAInfo);
43414337
if (!UniformBase) {
43424338
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
43434339
Index = getValue(Ptr);
@@ -4354,25 +4350,26 @@ void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
43544350
void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
43554351
SDLoc sdl = getCurSDLoc();
43564352

4357-
auto getMaskedLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4358-
unsigned& Alignment) {
4353+
auto getMaskedLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4354+
MaybeAlign &Alignment) {
43594355
// @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
43604356
Ptr = I.getArgOperand(0);
4361-
Alignment = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4357+
Alignment =
4358+
MaybeAlign(cast<ConstantInt>(I.getArgOperand(1))->getZExtValue());
43624359
Mask = I.getArgOperand(2);
43634360
Src0 = I.getArgOperand(3);
43644361
};
4365-
auto getExpandingLoadOps = [&](Value* &Ptr, Value* &Mask, Value* &Src0,
4366-
unsigned& Alignment) {
4362+
auto getExpandingLoadOps = [&](Value *&Ptr, Value *&Mask, Value *&Src0,
4363+
MaybeAlign &Alignment) {
43674364
// @llvm.masked.expandload.*(Ptr, Mask, Src0)
43684365
Ptr = I.getArgOperand(0);
4369-
Alignment = 0;
4366+
Alignment = None;
43704367
Mask = I.getArgOperand(1);
43714368
Src0 = I.getArgOperand(2);
43724369
};
43734370

43744371
Value *PtrOperand, *MaskOperand, *Src0Operand;
4375-
unsigned Alignment;
4372+
MaybeAlign Alignment;
43764373
if (IsExpanding)
43774374
getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
43784375
else
@@ -4385,7 +4382,7 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
43854382

43864383
EVT VT = Src0.getValueType();
43874384
if (!Alignment)
4388-
Alignment = DAG.getEVTAlignment(VT);
4385+
Alignment = DAG.getEVTAlign(VT);
43894386

43904387
AAMDNodes AAInfo;
43914388
I.getAAMetadata(AAInfo);
@@ -4403,14 +4400,11 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
44034400

44044401
SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode();
44054402

4406-
MachineMemOperand *MMO =
4407-
DAG.getMachineFunction().
4408-
getMachineMemOperand(MachinePointerInfo(PtrOperand),
4409-
MachineMemOperand::MOLoad,
4410-
// TODO: Make MachineMemOperands aware of scalable
4411-
// vectors.
4412-
VT.getStoreSize().getKnownMinSize(),
4413-
Alignment, AAInfo, Ranges);
4403+
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4404+
MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad,
4405+
// TODO: Make MachineMemOperands aware of scalable
4406+
// vectors.
4407+
VT.getStoreSize().getKnownMinSize(), *Alignment, AAInfo, Ranges);
44144408

44154409
SDValue Load =
44164410
DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Offset, Mask, Src0, VT, MMO,
@@ -4430,9 +4424,9 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
44304424

44314425
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
44324426
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4433-
unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
4427+
MaybeAlign Alignment(cast<ConstantInt>(I.getArgOperand(1))->getZExtValue());
44344428
if (!Alignment)
4435-
Alignment = DAG.getEVTAlignment(VT);
4429+
Alignment = DAG.getEVTAlign(VT);
44364430

44374431
AAMDNodes AAInfo;
44384432
I.getAAMetadata(AAInfo);
@@ -4445,14 +4439,11 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
44454439
SDValue Scale;
44464440
bool UniformBase = getUniformBase(Ptr, Base, Index, IndexType, Scale, this);
44474441
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
4448-
MachineMemOperand *MMO =
4449-
DAG.getMachineFunction().
4450-
getMachineMemOperand(MachinePointerInfo(AS),
4451-
MachineMemOperand::MOLoad,
4452-
// TODO: Make MachineMemOperands aware of scalable
4453-
// vectors.
4454-
MemoryLocation::UnknownSize,
4455-
Alignment, AAInfo, Ranges);
4442+
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
4443+
MachinePointerInfo(AS), MachineMemOperand::MOLoad,
4444+
// TODO: Make MachineMemOperands aware of scalable
4445+
// vectors.
4446+
MemoryLocation::UnknownSize, *Alignment, AAInfo, Ranges);
44564447

44574448
if (!UniformBase) {
44584449
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
@@ -4479,16 +4470,14 @@ void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
44794470
MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
44804471
SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
44814472

4482-
auto Alignment = DAG.getEVTAlignment(MemVT);
44834473
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
44844474
auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout());
44854475

44864476
MachineFunction &MF = DAG.getMachineFunction();
4487-
MachineMemOperand *MMO =
4488-
MF.getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
4489-
Flags, MemVT.getStoreSize(), Alignment,
4490-
AAMDNodes(), nullptr, SSID, SuccessOrdering,
4491-
FailureOrdering);
4477+
MachineMemOperand *MMO = MF.getMachineMemOperand(
4478+
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4479+
DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, SuccessOrdering,
4480+
FailureOrdering);
44924481

44934482
SDValue L = DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
44944483
dl, MemVT, VTs, InChain,
@@ -4527,15 +4516,13 @@ void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
45274516
SDValue InChain = getRoot();
45284517

45294518
auto MemVT = getValue(I.getValOperand()).getSimpleValueType();
4530-
auto Alignment = DAG.getEVTAlignment(MemVT);
45314519
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
45324520
auto Flags = TLI.getAtomicMemOperandFlags(I, DAG.getDataLayout());
45334521

45344522
MachineFunction &MF = DAG.getMachineFunction();
4535-
MachineMemOperand *MMO =
4536-
MF.getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), Flags,
4537-
MemVT.getStoreSize(), Alignment, AAMDNodes(),
4538-
nullptr, SSID, Ordering);
4523+
MachineMemOperand *MMO = MF.getMachineMemOperand(
4524+
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
4525+
DAG.getEVTAlign(MemVT), AAMDNodes(), nullptr, SSID, Ordering);
45394526

45404527
SDValue L =
45414528
DAG.getAtomic(NT, dl, MemVT, InChain,

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 19 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2176,32 +2176,33 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
21762176
// Rationale: This sequence saves uop updates compared to a sequence of
21772177
// pre-increment spills like stp xi,xj,[sp,#-16]!
21782178
// Note: Similar rationale and sequence for restores in epilog.
2179-
unsigned Size, Align;
2179+
unsigned Size;
2180+
Align Alignment;
21802181
switch (RPI.Type) {
21812182
case RegPairInfo::GPR:
21822183
StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
21832184
Size = 8;
2184-
Align = 8;
2185+
Alignment = Align(8);
21852186
break;
21862187
case RegPairInfo::FPR64:
21872188
StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
21882189
Size = 8;
2189-
Align = 8;
2190+
Alignment = Align(8);
21902191
break;
21912192
case RegPairInfo::FPR128:
21922193
StrOpc = RPI.isPaired() ? AArch64::STPQi : AArch64::STRQui;
21932194
Size = 16;
2194-
Align = 16;
2195+
Alignment = Align(16);
21952196
break;
21962197
case RegPairInfo::ZPR:
21972198
StrOpc = AArch64::STR_ZXI;
21982199
Size = 16;
2199-
Align = 16;
2200+
Alignment = Align(16);
22002201
break;
22012202
case RegPairInfo::PPR:
22022203
StrOpc = AArch64::STR_PXI;
22032204
Size = 2;
2204-
Align = 2;
2205+
Alignment = Align(2);
22052206
break;
22062207
}
22072208
LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
@@ -2230,16 +2231,16 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
22302231
MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));
22312232
MIB.addMemOperand(MF.getMachineMemOperand(
22322233
MachinePointerInfo::getFixedStack(MF, FrameIdxReg2),
2233-
MachineMemOperand::MOStore, Size, Align));
2234+
MachineMemOperand::MOStore, Size, Alignment));
22342235
}
22352236
MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))
22362237
.addReg(AArch64::SP)
22372238
.addImm(RPI.Offset) // [sp, #offset*scale],
22382239
// where factor*scale is implicit
22392240
.setMIFlag(MachineInstr::FrameSetup);
22402241
MIB.addMemOperand(MF.getMachineMemOperand(
2241-
MachinePointerInfo::getFixedStack(MF,FrameIdxReg1),
2242-
MachineMemOperand::MOStore, Size, Align));
2242+
MachinePointerInfo::getFixedStack(MF, FrameIdxReg1),
2243+
MachineMemOperand::MOStore, Size, Alignment));
22432244
if (NeedsWinCFI)
22442245
InsertSEH(MIB, TII, MachineInstr::FrameSetup);
22452246

@@ -2281,32 +2282,33 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
22812282
// ldp x22, x21, [sp, #0] // addImm(+0)
22822283
// Note: see comment in spillCalleeSavedRegisters()
22832284
unsigned LdrOpc;
2284-
unsigned Size, Align;
2285+
unsigned Size;
2286+
Align Alignment;
22852287
switch (RPI.Type) {
22862288
case RegPairInfo::GPR:
22872289
LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
22882290
Size = 8;
2289-
Align = 8;
2291+
Alignment = Align(8);
22902292
break;
22912293
case RegPairInfo::FPR64:
22922294
LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
22932295
Size = 8;
2294-
Align = 8;
2296+
Alignment = Align(8);
22952297
break;
22962298
case RegPairInfo::FPR128:
22972299
LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
22982300
Size = 16;
2299-
Align = 16;
2301+
Alignment = Align(16);
23002302
break;
23012303
case RegPairInfo::ZPR:
23022304
LdrOpc = AArch64::LDR_ZXI;
23032305
Size = 16;
2304-
Align = 16;
2306+
Alignment = Align(16);
23052307
break;
23062308
case RegPairInfo::PPR:
23072309
LdrOpc = AArch64::LDR_PXI;
23082310
Size = 2;
2309-
Align = 2;
2311+
Alignment = Align(2);
23102312
break;
23112313
}
23122314
LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
@@ -2329,7 +2331,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
23292331
MIB.addReg(Reg2, getDefRegState(true));
23302332
MIB.addMemOperand(MF.getMachineMemOperand(
23312333
MachinePointerInfo::getFixedStack(MF, FrameIdxReg2),
2332-
MachineMemOperand::MOLoad, Size, Align));
2334+
MachineMemOperand::MOLoad, Size, Alignment));
23332335
}
23342336
MIB.addReg(Reg1, getDefRegState(true))
23352337
.addReg(AArch64::SP)
@@ -2338,7 +2340,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
23382340
.setMIFlag(MachineInstr::FrameDestroy);
23392341
MIB.addMemOperand(MF.getMachineMemOperand(
23402342
MachinePointerInfo::getFixedStack(MF, FrameIdxReg1),
2341-
MachineMemOperand::MOLoad, Size, Align));
2343+
MachineMemOperand::MOLoad, Size, Alignment));
23422344
if (NeedsWinCFI)
23432345
InsertSEH(MIB, TII, MachineInstr::FrameDestroy);
23442346
};

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