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[AArch64] Tests for showing MachineCombiner COPY patterns. NFC
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‎llvm/test/CodeGen/AArch64/machine-combiner-copy.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnuabi -mattr=+fullfp16 -O3 | FileCheck %s
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define void @fma_dup_f16(ptr noalias nocapture noundef readonly %A, half noundef %B, ptr noalias nocapture noundef %C, i32 noundef %n) {
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; CHECK-LABEL: fma_dup_f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
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; CHECK-NEXT: cbz w2, .LBB0_8
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; CHECK-NEXT: // %bb.1: // %for.body.preheader
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; CHECK-NEXT: mov w8, w2
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; CHECK-NEXT: cmp w2, #15
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; CHECK-NEXT: b.hi .LBB0_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov x9, xzr
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; CHECK-NEXT: b .LBB0_6
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; CHECK-NEXT: .LBB0_3: // %vector.ph
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; CHECK-NEXT: and x9, x8, #0xfffffff0
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; CHECK-NEXT: add x10, x1, #16
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; CHECK-NEXT: add x11, x0, #16
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; CHECK-NEXT: mov x12, x9
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; CHECK-NEXT: dup v1.8h, v0.h[0]
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; CHECK-NEXT: .LBB0_4: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldp q2, q3, [x11, #-16]
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; CHECK-NEXT: subs x12, x12, #16
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; CHECK-NEXT: add x11, x11, #32
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; CHECK-NEXT: ldp q4, q5, [x10, #-16]
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; CHECK-NEXT: fmla v4.8h, v2.8h, v1.8h
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; CHECK-NEXT: fmla v5.8h, v3.8h, v0.h[0]
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; CHECK-NEXT: stp q4, q5, [x10, #-16]
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; CHECK-NEXT: add x10, x10, #32
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; CHECK-NEXT: b.ne .LBB0_4
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; CHECK-NEXT: // %bb.5: // %middle.block
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: b.eq .LBB0_8
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; CHECK-NEXT: .LBB0_6: // %for.body.preheader1
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; CHECK-NEXT: lsl x10, x9, #1
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; CHECK-NEXT: sub x8, x8, x9
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; CHECK-NEXT: add x9, x1, x10
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; CHECK-NEXT: add x10, x0, x10
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; CHECK-NEXT: .LBB0_7: // %for.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr h1, [x10], #2
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; CHECK-NEXT: ldr h2, [x9]
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; CHECK-NEXT: subs x8, x8, #1
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; CHECK-NEXT: fmadd h1, h1, h0, h2
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; CHECK-NEXT: str h1, [x9], #2
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; CHECK-NEXT: b.ne .LBB0_7
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; CHECK-NEXT: .LBB0_8: // %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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%cmp6.not = icmp eq i32 %n, 0
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br i1 %cmp6.not, label %for.cond.cleanup, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %n to i64
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%min.iters.check = icmp ult i32 %n, 16
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br i1 %min.iters.check, label %for.body.preheader14, label %vector.ph
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vector.ph: ; preds = %for.body.preheader
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%n.vec = and i64 %wide.trip.count, 4294967280
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%broadcast.splatinsert = insertelement <8 x half> poison, half %B, i64 0
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%broadcast.splat = shufflevector <8 x half> %broadcast.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
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%broadcast.splatinsert10 = insertelement <8 x half> poison, half %B, i64 0
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%broadcast.splat11 = shufflevector <8 x half> %broadcast.splatinsert10, <8 x half> poison, <8 x i32> zeroinitializer
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds half, ptr %A, i64 %index
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%wide.load = load <8 x half>, ptr %0, align 2
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%1 = getelementptr inbounds half, ptr %0, i64 8
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%wide.load9 = load <8 x half>, ptr %1, align 2
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%2 = fmul fast <8 x half> %wide.load, %broadcast.splat
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%3 = fmul fast <8 x half> %wide.load9, %broadcast.splat11
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%4 = getelementptr inbounds half, ptr %C, i64 %index
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%wide.load12 = load <8 x half>, ptr %4, align 2
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%5 = getelementptr inbounds half, ptr %4, i64 8
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%wide.load13 = load <8 x half>, ptr %5, align 2
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%6 = fadd fast <8 x half> %wide.load12, %2
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%7 = fadd fast <8 x half> %wide.load13, %3
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store <8 x half> %6, ptr %4, align 2
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store <8 x half> %7, ptr %5, align 2
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%index.next = add nuw i64 %index, 16
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%8 = icmp eq i64 %index.next, %n.vec
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br i1 %8, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i64 %n.vec, %wide.trip.count
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br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader14
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for.body.preheader14: ; preds = %for.body.preheader, %middle.block
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%indvars.iv.ph = phi i64 [ 0, %for.body.preheader ], [ %n.vec, %middle.block ]
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %middle.block, %entry
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ret void
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for.body: ; preds = %for.body.preheader14, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %indvars.iv.ph, %for.body.preheader14 ]
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%arrayidx = getelementptr inbounds half, ptr %A, i64 %indvars.iv
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%9 = load half, ptr %arrayidx, align 2
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%mul = fmul fast half %9, %B
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%arrayidx2 = getelementptr inbounds half, ptr %C, i64 %indvars.iv
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%10 = load half, ptr %arrayidx2, align 2
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%add = fadd fast half %10, %mul
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store half %add, ptr %arrayidx2, align 2
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}

‎llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir

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br label %for.cond
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}
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define void @extracopy(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, <2 x float>* %ret) #0 {
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unreachable
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}
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attributes #0 = { "target-cpu"="cortex-a57" }
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...
@@ -545,3 +549,71 @@ body: |
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B %bb.1
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...
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---
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name: extracopy
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr64 }
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- { id: 1, class: fpr64 }
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- { id: 2, class: fpr64 }
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- { id: 3, class: fpr64 }
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- { id: 4, class: gpr64common }
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- { id: 5, class: fpr64 }
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- { id: 6, class: fpr64 }
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- { id: 7, class: fpr128 }
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- { id: 8, class: fpr128 }
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- { id: 9, class: fpr64 }
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- { id: 10, class: fpr64 }
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- { id: 11, class: fpr64 }
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liveins:
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- { reg: '$d0', virtual-reg: '%1' }
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- { reg: '$d1', virtual-reg: '%2' }
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- { reg: '$d2', virtual-reg: '%3' }
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- { reg: '$x0', virtual-reg: '%4' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: extracopy
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; CHECK: bb.0:
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; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]
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; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane killed [[INSERT_SUBREG]], 0
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY5]], [[COPY6]]
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; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2f32_]], [[COPY4]]
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; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16)
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; CHECK-NEXT: B %bb.1
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bb.0:
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liveins: $d0, $d1, $d2, $x0
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%4:gpr64common = COPY $x0
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%3:fpr64 = COPY $d2
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%2:fpr64 = COPY $d1
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%1:fpr64 = COPY $d0
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%8:fpr128 = IMPLICIT_DEF
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%7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub
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%6:fpr64 = COPY %3
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%5:fpr64 = COPY %2
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%11:fpr64 = DUPv2i32lane killed %7, 0
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%0:fpr64 = COPY %11
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bb.1:
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%9:fpr64 = FMULv2f32 %5, %0
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%10:fpr64 = FADDv2f32 killed %9, %6
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STRDui killed %10, %4, 0 :: (store 8, align 16)
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B %bb.1
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...

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