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[X86] combineConcatVectorOps - convert X86ISD::PALIGNR concatenation to use combineConcatVectorOps recursion (#130572)
Only concatenate X86ISD::PALIGNR nodes if at least one operand is beneficial to concatenate
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2 files changed

+11
-9
lines changed

2 files changed

+11
-9
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58443,9 +58443,13 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
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llvm::all_of(Ops, [Op0](SDValue Op) {
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return Op0.getOperand(2) == Op.getOperand(2);
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})) {
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return DAG.getNode(Op0.getOpcode(), DL, VT,
58447-
ConcatSubOperand(VT, Ops, 0),
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ConcatSubOperand(VT, Ops, 1), Op0.getOperand(2));
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SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
58447+
SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
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if (Concat0 || Concat1)
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return DAG.getNode(Op0.getOpcode(), DL, VT,
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Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
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Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 1),
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Op0.getOperand(2));
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}
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break;
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case X86ISD::BLENDI:

llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -775,15 +775,13 @@ define <32 x i8> @combine_pshufb_pshufb_or_pshufb(<32 x i8> %a0) {
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ret <32 x i8> %4
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}
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778-
; TODO: Not beneficial to concatenate both inputs just to create a 256-bit palignr
778+
; Not beneficial to concatenate both inputs just to create a 256-bit palignr
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define <32 x i8> @concat_alignr_unnecessary(<16 x i8> %a0, <16 x i8> noundef %a1, <16 x i8> %a2) nounwind {
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; CHECK-LABEL: concat_alignr_unnecessary:
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; CHECK: # %bb.0:
782-
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
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; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
785-
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: vpalignr {{.*#+}} ymm0 = ymm1[3,4,5,6,7,8,9,10,11,12,13,14,15],ymm0[0,1,2],ymm1[19,20,21,22,23,24,25,26,27,28,29,30,31],ymm0[16,17,18]
782+
; CHECK-NEXT: vpalignr {{.*#+}} xmm1 = xmm1[3,4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2]
783+
; CHECK-NEXT: vpalignr {{.*#+}} xmm0 = xmm2[3,4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0,1,2]
784+
; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
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; CHECK-NEXT: ret{{[l|q]}}
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%lo = shufflevector <16 x i8> %a1, <16 x i8> %a0, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
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%hi = shufflevector <16 x i8> %a2, <16 x i8> %a0, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>

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