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[TableGen] Fix concatenation of subreg and artificial subregs (#114391)
When CoveredBySubRegs is true and a sub-register consists of two parts; a regular subreg and an artificial subreg, then TableGen should consider only concatenating the non-artificial subregs. For example, S0_S1 is a concatenated subreg from D0_D1, but S0_S1_HI should not be considered.
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‎llvm/test/TableGen/ArtificialSubregs.td

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// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK
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include "llvm/Target/Target.td"
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// This file tests that when using `isArtificial` for subregisters in
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// combination with `CoveredBySubRegs`, that TableGen infers the
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// correct register classes, subregisters and lane masks, especially
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// when the registers (that consist partially from artificial subregs)
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// are used in tuples.
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//
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// The register hierarchy that this test implements is:
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//
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// ssub_hi ssub
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// \ /
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// dsub
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// dsub_hi /
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// \ /
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// qsub
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//
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// Where the _hi parts are artificial and where subregs ssub, dsub and qsub
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// are all addressable as real registers.
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//
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// These are then used in {S0, S1, S2}, {D0, D1, D2} and {Q0, Q1, Q2},
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// from which tuples are created.
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class MyReg<string n, list<Register> subregs = []>
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: Register<n> {
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let Namespace = "Test";
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let SubRegs = subregs;
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"Test", types, size, registers> {
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let Size = size;
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}
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def ssub : SubRegIndex< 32, 0>;
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def ssub_hi : SubRegIndex< 32, 32>;
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def dsub : SubRegIndex< 64, 0>;
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def dsub_hi : SubRegIndex< 64, 64>;
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def qsub : SubRegIndex<128, 0>;
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def S0 : MyReg<"s0">;
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def S1 : MyReg<"s1">;
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def S2 : MyReg<"s2">;
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let isArtificial = 1 in {
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def S0_HI : MyReg<"s0_hi">;
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def S1_HI : MyReg<"s1_hi">;
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def S2_HI : MyReg<"s2_hi">;
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def D0_HI : MyReg<"D0_hi">;
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def D1_HI : MyReg<"D1_hi">;
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def D2_HI : MyReg<"D2_hi">;
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}
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let SubRegIndices = [ssub, ssub_hi], CoveredBySubRegs = 1 in {
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def D0 : MyReg<"d0", [S0, S0_HI]>;
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def D1 : MyReg<"d1", [S1, S1_HI]>;
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def D2 : MyReg<"d2", [S2, S2_HI]>;
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}
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let SubRegIndices = [dsub, dsub_hi], CoveredBySubRegs = 1 in {
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def Q0 : MyReg<"q0", [D0, D0_HI]>;
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def Q1 : MyReg<"q1", [D1, D1_HI]>;
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def Q2 : MyReg<"q2", [D2, D2_HI]>;
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}
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def SRegs : MyClass<32, [i32], (sequence "S%u", 0, 2)>;
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def DRegs : MyClass<64, [i64], (sequence "D%u", 0, 2)>;
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def QRegs : MyClass<128, [i128], (sequence "Q%u", 0, 2)>;
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def dsub0 : SubRegIndex<64>;
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def dsub1 : SubRegIndex<64>;
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def dsub2 : SubRegIndex<64>;
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def ssub0 : SubRegIndex<32>;
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def ssub1 : ComposedSubRegIndex<dsub1, ssub>;
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def ssub2 : ComposedSubRegIndex<dsub2, ssub>;
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def STuples2 : RegisterTuples<[ssub0, ssub1],
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[(shl SRegs, 0), (shl SRegs, 1)]>;
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def STuplesRC2 : MyClass<64, [untyped], (add STuples2)>;
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def DTuples2 : RegisterTuples<[dsub0, dsub1],
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[(shl DRegs, 0), (shl DRegs, 1)]>;
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def DTuplesRC2 : MyClass<128, [untyped], (add DTuples2)>;
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def STuples3 : RegisterTuples<[ssub0, ssub1, ssub2],
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[(shl SRegs, 0), (shl SRegs, 1), (shl SRegs, 2)]>;
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def STuplesRC3 : MyClass<96, [untyped], (add STuples3)>;
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def DTuples3 : RegisterTuples<[dsub0, dsub1, dsub2],
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[(shl DRegs, 0), (shl DRegs, 1), (shl DRegs, 2)]>;
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def DTuplesRC3 : MyClass<192, [untyped], (add DTuples3)>;
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def TestTarget : Target;
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// CHECK: RegisterClass SRegs:
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// CHECK: LaneMask: 0000000000000001
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// CHECK: HasDisjunctSubRegs: 0
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// CHECK: CoveredBySubRegs: 0
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// CHECK: Regs: S0 S1 S2
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// CHECK: SubClasses: SRegs
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// CHECK: SuperClasses:
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//
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// CHECK: RegisterClass DRegs:
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// CHECK: LaneMask: 0000000000000004
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: CoveredBySubRegs: 1
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// CHECK: Regs: D0 D1 D2
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// CHECK: SubClasses: DRegs
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// CHECK: SuperClasses:
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//
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// CHECK: RegisterClass QRegs:
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// CHECK: LaneMask: 0000000000000044
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: CoveredBySubRegs: 1
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// CHECK: Regs: Q0 Q1 Q2
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// CHECK: SubClasses: QRegs
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// CHECK: SuperClasses:
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//
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// CHECK: SubRegIndex dsub:
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// CHECK-NEXT: LaneMask: 0000000000000044
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// CHECK: SubRegIndex dsub0:
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// CHECK-NEXT: LaneMask: 0000000000000044
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// CHECK: SubRegIndex dsub1:
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// CHECK-NEXT: LaneMask: 0000000000000090
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// CHECK: SubRegIndex dsub2:
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// CHECK-NEXT: LaneMask: 0000000000000120
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// CHECK: SubRegIndex dsub_hi:
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// CHECK-NEXT: LaneMask: 0000000000000001
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// CHECK: SubRegIndex ssub:
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// CHECK-NEXT: LaneMask: 0000000000000004
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// CHECK: SubRegIndex ssub0:
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// CHECK-NEXT: LaneMask: 0000000000000008
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// CHECK: SubRegIndex ssub1:
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// CHECK-NEXT: LaneMask: 0000000000000010
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// CHECK: SubRegIndex ssub2:
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// CHECK-NEXT: LaneMask: 0000000000000020
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// CHECK: SubRegIndex ssub_hi:
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// CHECK-NEXT: LaneMask: 0000000000000040
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// CHECK: SubRegIndex dsub1_then_ssub_hi:
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// CHECK-NEXT: LaneMask: 0000000000000080
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// CHECK: SubRegIndex dsub2_then_ssub_hi:
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// CHECK-NEXT: LaneMask: 0000000000000100
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// CHECK: SubRegIndex ssub_ssub1:
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// CHECK-NEXT: LaneMask: 0000000000000014
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// CHECK: SubRegIndex dsub0_dsub1:
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// CHECK-NEXT: LaneMask: 00000000000000D4
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// CHECK: SubRegIndex dsub1_dsub2:
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// CHECK-NEXT: LaneMask: 00000000000001B0
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// CHECK: SubRegIndex ssub_ssub1_ssub2:
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// CHECK-NEXT: LaneMask: 0000000000000034
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// CHECK: SubRegIndex ssub1_ssub2:
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// CHECK-NEXT: LaneMask: 0000000000000030
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// CHECK: SubRegIndex ssub0_ssub1:
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// CHECK-NEXT: LaneMask: 0000000000000018
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// CHECK: Register D0:
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// CHECK: CoveredBySubregs: 1
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: SubReg ssub = S0
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// CHECK: SubReg ssub_hi = S0_HI
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//
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// CHECK: Register Q0:
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// CHECK: CoveredBySubregs: 1
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: SubReg dsub = D0
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// CHECK: SubReg dsub_hi = D0_HI
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// CHECK: SubReg ssub = S0
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// CHECK: SubReg ssub_hi = S0_HI
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//
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// CHECK: Register S0:
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// CHECK: CoveredBySubregs: 0
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// CHECK: HasDisjunctSubRegs: 0
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//
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// CHECK: Register D0_D1:
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// CHECK: CoveredBySubregs: 1
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: SubReg dsub0 = D0
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// CHECK: SubReg dsub1 = D1
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// CHECK: SubReg ssub = S0
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// CHECK: SubReg ssub1 = S1
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// CHECK: SubReg ssub_hi = S0_HI
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// CHECK: SubReg dsub1_then_ssub_hi = S1_HI
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// CHECK: SubReg ssub_ssub1 = S0_S1
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//
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// CHECK: Register D0_D1_D2:
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// CHECK: CoveredBySubregs: 1
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: SubReg dsub0 = D0
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// CHECK: SubReg dsub1 = D1
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// CHECK: SubReg dsub2 = D2
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// CHECK: SubReg ssub = S0
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// CHECK: SubReg ssub1 = S1
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// CHECK: SubReg ssub2 = S2
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// CHECK: SubReg ssub_hi = S0_HI
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// CHECK: SubReg dsub1_then_ssub_hi = S1_HI
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// CHECK: SubReg dsub2_then_ssub_hi = S2_HI
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// CHECK: SubReg ssub_ssub1 = S0_S1
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// CHECK: SubReg dsub0_dsub1 = D0_D1
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// CHECK: SubReg dsub1_dsub2 = D1_D2
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// CHECK: SubReg ssub_ssub1_ssub2 = S0_S1_S2
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// CHECK: SubReg ssub1_ssub2 = S1_S2
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//
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// CHECK: Register S0_S1:
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// CHECK: CoveredBySubregs: 1
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: SubReg ssub0 = S0
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// CHECK: SubReg ssub1 = S1
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//
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// CHECK: Register S0_S1_S2:
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// CHECK: CoveredBySubregs: 1
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// CHECK: HasDisjunctSubRegs: 1
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// CHECK: SubReg ssub0 = S0
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// CHECK: SubReg ssub1 = S1
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// CHECK: SubReg ssub2 = S2
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// CHECK: SubReg ssub1_ssub2 = S1_S2
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// CHECK: SubReg ssub0_ssub1 = S0_S1

‎llvm/utils/TableGen/Common/CodeGenRegisters.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -399,18 +399,24 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
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// user already specified.
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for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
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CodeGenRegister *SR = ExplicitSubRegs[i];
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if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 ||
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SR->Artificial)
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if (!SR->CoveredBySubRegs || SR->Artificial)
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continue;
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// SR is composed of multiple sub-regs. Find their names in this register.
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bool AnyArtificial = false;
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SmallVector<CodeGenSubRegIndex *, 8> Parts;
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for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) {
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CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j];
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if (!I.Artificial)
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Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
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if (I.Artificial) {
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AnyArtificial = true;
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break;
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}
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Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
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}
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if (AnyArtificial)
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continue;
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// Offer this as an existing spelling for the concatenation of Parts.
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CodeGenSubRegIndex &Idx = *ExplicitSubRegIndices[i];
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Idx.setConcatenationOf(Parts);

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