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[GISel] Restrict G_BSWAP to multiples of 16 bits. (#70245)
This is consistent with the IR verifier and SelectionDAG's getNode. Update tests accordingly. I tried to keep some coverage of non-pow2 when possible. X86 didn't like a G_UNMERGE_VALUES from s48 to 3 s16 that got created when I tried s48.
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-136
lines changed

5 files changed

+77
-136
lines changed

‎llvm/lib/CodeGen/MachineVerifier.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1592,6 +1592,12 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
15921592
report("G_SEXT_INREG size must be less than source bit width", MI);
15931593
break;
15941594
}
1595+
case TargetOpcode::G_BSWAP: {
1596+
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1597+
if (DstTy.getScalarSizeInBits() % 16 != 0)
1598+
report("G_BSWAP size must be a multiple of 16 bits", MI);
1599+
break;
1600+
}
15951601
case TargetOpcode::G_SHUFFLE_VECTOR: {
15961602
const MachineOperand &MaskOp = MI->getOperand(3);
15971603
if (!MaskOp.isShuffleMask()) {

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir

Lines changed: 15 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -110,48 +110,27 @@ body: |
110110
RET_ReallyLR implicit $q0
111111
...
112112
---
113-
name: bswap_s88
113+
name: bswap_s80
114114
tracksRegLiveness: true
115115
body: |
116116
bb.0:
117117
liveins: $x0
118-
; CHECK-LABEL: name: bswap_s88
118+
; CHECK-LABEL: name: bswap_s80
119119
; CHECK: liveins: $x0
120-
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
121-
; CHECK: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[DEF]]
122-
; CHECK: [[BSWAP1:%[0-9]+]]:_(s64) = G_BSWAP [[DEF]]
123-
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
124-
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
125-
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
126-
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[BSWAP1]], [[C1]](s64)
127-
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
128-
; CHECK: $x0 = COPY [[OR]](s64)
129-
; CHECK: RET_ReallyLR implicit $x0
130-
%val:_(s88) = G_IMPLICIT_DEF
131-
%bswap:_(s88) = G_BSWAP %val
120+
; CHECK-NEXT: {{ $}}
121+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
122+
; CHECK-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[DEF]]
123+
; CHECK-NEXT: [[BSWAP1:%[0-9]+]]:_(s64) = G_BSWAP [[DEF]]
124+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
125+
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
126+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
127+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[BSWAP1]], [[C1]](s64)
128+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
129+
; CHECK-NEXT: $x0 = COPY [[OR]](s64)
130+
; CHECK-NEXT: RET_ReallyLR implicit $x0
131+
%val:_(s80) = G_IMPLICIT_DEF
132+
%bswap:_(s80) = G_BSWAP %val
132133
%trunc:_(s64) = G_TRUNC %bswap
133134
$x0 = COPY %trunc(s64)
134135
RET_ReallyLR implicit $x0
135136
...
136-
---
137-
name: bswap_s4
138-
tracksRegLiveness: true
139-
body: |
140-
bb.0:
141-
liveins: $x0
142-
; CHECK-LABEL: name: bswap_s4
143-
; CHECK: liveins: $x0
144-
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
145-
; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[DEF]]
146-
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 28
147-
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
148-
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
149-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
150-
; CHECK: %ext:_(s64) = G_AND [[ANYEXT]], [[C1]]
151-
; CHECK: $x0 = COPY %ext(s64)
152-
; CHECK: RET_ReallyLR implicit $x0
153-
%val:_(s4) = G_IMPLICIT_DEF
154-
%bswap:_(s4) = G_BSWAP %val
155-
%ext:_(s64) = G_ZEXT %bswap
156-
$x0 = COPY %ext(s64)
157-
RET_ReallyLR implicit $x0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir

Lines changed: 36 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -2,42 +2,6 @@
22
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s
33
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX8 %s
44

5-
---
6-
name: bswap_s8
7-
8-
body: |
9-
bb.0:
10-
liveins: $vgpr0
11-
; GFX7-LABEL: name: bswap_s8
12-
; GFX7: liveins: $vgpr0
13-
; GFX7-NEXT: {{ $}}
14-
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15-
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
16-
; GFX7-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
17-
; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
18-
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
19-
; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
20-
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
21-
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
22-
; GFX7-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
23-
; GFX7-NEXT: $vgpr0 = COPY [[OR]](s32)
24-
; GFX8-LABEL: name: bswap_s8
25-
; GFX8: liveins: $vgpr0
26-
; GFX8-NEXT: {{ $}}
27-
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
28-
; GFX8-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
29-
; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s16) = G_BSWAP [[TRUNC]]
30-
; GFX8-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
31-
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[BSWAP]], [[C]](s16)
32-
; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
33-
; GFX8-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
34-
%0:_(s32) = COPY $vgpr0
35-
%1:_(s8) = G_TRUNC %0
36-
%2:_(s8) = G_BSWAP %1
37-
%3:_(s32) = G_ANYEXT %2
38-
$vgpr0 = COPY %3
39-
...
40-
415
---
426
name: bswap_s16
437

@@ -74,40 +38,6 @@ body: |
7438
$vgpr0 = COPY %3
7539
...
7640

77-
---
78-
name: bswap_s24
79-
80-
body: |
81-
bb.0:
82-
liveins: $vgpr0
83-
; GFX7-LABEL: name: bswap_s24
84-
; GFX7: liveins: $vgpr0
85-
; GFX7-NEXT: {{ $}}
86-
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
87-
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
88-
; GFX7-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
89-
; GFX7-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
90-
; GFX7-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
91-
; GFX7-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
92-
; GFX7-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
93-
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
94-
; GFX7-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
95-
; GFX7-NEXT: $vgpr0 = COPY [[OR]](s32)
96-
; GFX8-LABEL: name: bswap_s24
97-
; GFX8: liveins: $vgpr0
98-
; GFX8-NEXT: {{ $}}
99-
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
100-
; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
101-
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
102-
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
103-
; GFX8-NEXT: $vgpr0 = COPY [[LSHR]](s32)
104-
%0:_(s32) = COPY $vgpr0
105-
%1:_(s24) = G_TRUNC %0
106-
%2:_(s24) = G_BSWAP %1
107-
%3:_(s32) = G_ANYEXT %2
108-
$vgpr0 = COPY %3
109-
...
110-
11141
---
11242
name: bswap_s32
11343

@@ -438,3 +368,39 @@ body: |
438368
%1:_(<2 x s64>) = G_BSWAP %0
439369
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
440370
...
371+
372+
---
373+
name: bswap_s48
374+
375+
body: |
376+
bb.0:
377+
liveins: $vgpr0_vgpr1
378+
; GFX7-LABEL: name: bswap_s48
379+
; GFX7: liveins: $vgpr0_vgpr1
380+
; GFX7-NEXT: {{ $}}
381+
; GFX7-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
382+
; GFX7-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
383+
; GFX7-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[UV1]]
384+
; GFX7-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[UV]]
385+
; GFX7-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BSWAP]](s32), [[BSWAP1]](s32)
386+
; GFX7-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
387+
; GFX7-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C]](s32)
388+
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
389+
;
390+
; GFX8-LABEL: name: bswap_s48
391+
; GFX8: liveins: $vgpr0_vgpr1
392+
; GFX8-NEXT: {{ $}}
393+
; GFX8-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
394+
; GFX8-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
395+
; GFX8-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[UV1]]
396+
; GFX8-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[UV]]
397+
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BSWAP]](s32), [[BSWAP1]](s32)
398+
; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
399+
; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV]], [[C]](s32)
400+
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
401+
%0:_(s64) = COPY $vgpr0_vgpr1
402+
%1:_(s48) = G_TRUNC %0
403+
%2:_(s48) = G_BSWAP %1
404+
%3:_(s64) = G_ANYEXT %2
405+
$vgpr0_vgpr1 = COPY %3
406+
...

‎llvm/test/CodeGen/X86/GlobalISel/legalize-bswap.mir

Lines changed: 1 addition & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2,37 +2,8 @@
22
# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=X86-32
33
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=X86-64
44

5-
# test bswap for s16, s17, s32, and s64
5+
# test bswap for s16, s32, and s64
66

7-
...
8-
---
9-
name: test_bswap17
10-
body: |
11-
bb.1:
12-
; X86-32-LABEL: name: test_bswap17
13-
; X86-32: [[DEF:%[0-9]+]]:_(s17) = IMPLICIT_DEF
14-
; X86-32-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s17)
15-
; X86-32-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT]]
16-
; X86-32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 15
17-
; X86-32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s8)
18-
; X86-32-NEXT: [[TRUNC:%[0-9]+]]:_(s17) = G_TRUNC [[LSHR]](s32)
19-
; X86-32-NEXT: [[COPY:%[0-9]+]]:_(s17) = COPY [[TRUNC]](s17)
20-
; X86-32-NEXT: RET 0, implicit [[COPY]](s17)
21-
; X86-64-LABEL: name: test_bswap17
22-
; X86-64: [[DEF:%[0-9]+]]:_(s17) = IMPLICIT_DEF
23-
; X86-64-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s17)
24-
; X86-64-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ANYEXT]]
25-
; X86-64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 15
26-
; X86-64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s8)
27-
; X86-64-NEXT: [[TRUNC:%[0-9]+]]:_(s17) = G_TRUNC [[LSHR]](s32)
28-
; X86-64-NEXT: [[COPY:%[0-9]+]]:_(s17) = COPY [[TRUNC]](s17)
29-
; X86-64-NEXT: RET 0, implicit [[COPY]](s17)
30-
%0:_(s17) = IMPLICIT_DEF
31-
%1:_(s17) = G_BSWAP %0
32-
%2:_(s17) = COPY %1(s17)
33-
RET 0, implicit %2
34-
35-
...
367
---
378
name: test_bswap64
389
body: |

‎llvm/test/MachineVerifier/test_g_bswap.mir

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
#RUN: not --crash llc -mtriple=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
2+
# REQUIRES: aarch64-registered-target
3+
4+
---
5+
name: test_bswap
6+
legalized: true
7+
regBankSelected: false
8+
selected: false
9+
tracksRegLiveness: true
10+
liveins:
11+
body: |
12+
bb.0:
13+
14+
%0:_(s17) = G_CONSTANT i32 17
15+
16+
; CHECK: Bad machine code: G_BSWAP size must be a multiple of 16 bits
17+
%1:_(s17) = G_BSWAP %0
18+
19+
...

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