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[lldb][AArch64][Linux] Add register field information for SME's SVCR register (#71809)
This register is a pseudo register but mirrors the architectural register's contents. See: https://developer.arm.com/documentation/ddi0616/latest/ For the full details. Example output: ``` (lldb) register read svcr svcr = 0x0000000000000002 = (ZA = 1, SM = 0) ```
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4 files changed

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lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,19 @@
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using namespace lldb_private;
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LinuxArm64RegisterFlags::Fields
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LinuxArm64RegisterFlags::DetectSVCRFields(uint64_t hwcap, uint64_t hwcap2) {
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(void)hwcap;
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(void)hwcap2;
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// Represents the pseudo register that lldb-server builds, which itself
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// matches the architectural register SCVR. The fields match SVCR in the Arm
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// manual.
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return {
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{"ZA", 1},
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{"SM", 0},
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};
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}
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LinuxArm64RegisterFlags::Fields
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LinuxArm64RegisterFlags::DetectMTECtrlFields(uint64_t hwcap, uint64_t hwcap2) {
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(void)hwcap;

lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ class LinuxArm64RegisterFlags {
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static Fields DetectFPSRFields(uint64_t hwcap, uint64_t hwcap2);
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static Fields DetectFPCRFields(uint64_t hwcap, uint64_t hwcap2);
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static Fields DetectMTECtrlFields(uint64_t hwcap, uint64_t hwcap2);
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static Fields DetectSVCRFields(uint64_t hwcap, uint64_t hwcap2);
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struct RegisterEntry {
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RegisterEntry(llvm::StringRef name, unsigned size, DetectorFn detector)
@@ -68,11 +69,12 @@ class LinuxArm64RegisterFlags {
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llvm::StringRef m_name;
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RegisterFlags m_flags;
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DetectorFn m_detector;
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} m_registers[4] = {
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} m_registers[5] = {
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RegisterEntry("cpsr", 4, DetectCPSRFields),
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RegisterEntry("fpsr", 4, DetectFPSRFields),
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RegisterEntry("fpcr", 4, DetectFPCRFields),
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RegisterEntry("mte_ctrl", 8, DetectMTECtrlFields),
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RegisterEntry("svcr", 8, DetectSVCRFields),
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};
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// Becomes true once field detection has been run for all registers.

lldb/test/API/commands/register/register/aarch64_sme_z_registers/save_restore/TestSMEZRegistersSaveRestore.py

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -180,9 +180,12 @@ def za_expr_test_impl(self, sve_mode, za_state, swap_start_vl):
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self.runCmd("register read " + sve_reg_names)
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sve_values = self.res.GetOutput()
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svcr_value = 1 if sve_mode == Mode.SSVE else 0
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if za_state == ZA.Enabled:
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svcr_value += 2
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za = 1 if za_state == ZA.Enabled else 0
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sm = 1 if sve_mode == Mode.SSVE else 0
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svcr_value = "0x{:016x}".format((za << 1) | sm)
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expected_svcr = [svcr_value]
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if self.hasXMLSupport():
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expected_svcr.append("(ZA = {}, SM = {})".format(za, sm))
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has_zt0 = self.isAArch64SME2()
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@@ -201,7 +204,8 @@ def check_regs():
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self.assertEqual(start_vg, self.read_vg())
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self.expect("register read " + sve_reg_names, substrs=[sve_values])
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self.expect("register read svcr", substrs=["0x{:016x}".format(svcr_value)])
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self.expect("register read svcr", substrs=expected_svcr)
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for expr in exprs:
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expr_cmd = "expression {}()".format(expr)

lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,17 +5,17 @@
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import lldb
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import itertools
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from enum import Enum
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from enum import IntEnum
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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class Mode(Enum):
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class Mode(IntEnum):
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SVE = 0
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SSVE = 1
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class ZA(Enum):
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class ZA(IntEnum):
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Disabled = 0
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Enabled = 1
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@@ -56,7 +56,12 @@ def check_corefile(self, corefile):
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svcr = 1 if sve_mode == Mode.SSVE else 0
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if za == ZA.Enabled:
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svcr |= 2
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self.expect("register read svcr", substrs=["0x{:016x}".format(svcr)])
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expected_svcr = ["0x{:016x}".format(svcr)]
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if self.hasXMLSupport():
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expected_svcr.append("(ZA = {:d}, SM = {})".format(za, sve_mode))
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self.expect("register read svcr", substrs=expected_svcr)
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repeat_bytes = lambda v, n: " ".join(["0x{:02x}".format(v)] * n)
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