Address reviewer's comments

Author: mshockwave

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1785,6 +1785,8 @@ bool RISCVInstrInfo::hasReassociableVectorSibling(const MachineInstr &Inst,
                                                   bool &Commuted) const {
   const MachineBasicBlock *MBB = Inst.getParent();
   const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
+  assert(RISCVII::isFirstDefTiedToFirstUse(get(Inst.getOpcode())) &&
+         "Expect the present of passthrough operand.");
   MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
   MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(3).getReg());