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[RISCV] Merge DecoderNamespace for CORE-V extensions. NFC
Similar to Qualcomm, Sifive, T-Head, and Rivos extensions.
1 parent 0230d63 commit 9b066f0

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2 files changed

+24
-30
lines changed

2 files changed

+24
-30
lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -644,6 +644,12 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
644644
#define TRY_TO_DECODE_FEATURE_ANY(FEATURES, DECODER_TABLE, DESC) \
645645
TRY_TO_DECODE((STI.getFeatureBits() & (FEATURES)).any(), DECODER_TABLE, DESC)
646646

647+
static constexpr FeatureBitset XCVFeatureGroup = {
648+
RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
649+
RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
650+
RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
651+
RISCV::FeatureVendorXCVbi};
652+
647653
static constexpr FeatureBitset XRivosFeatureGroup = {
648654
RISCV::FeatureVendorXRivosVisni,
649655
RISCV::FeatureVendorXRivosVizip,
@@ -701,20 +707,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
701707
"MIPS mips.lsp");
702708
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSCMove,
703709
DecoderTableXmipscmove32, "MIPS mips.ccmov");
704-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
705-
DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation");
706-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
707-
"CORE-V Event load");
708-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
709-
"CORE-V MAC");
710-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
711-
"CORE-V MEM");
712-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
713-
"CORE-V ALU");
714-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
715-
"CORE-V SIMD extensions");
716-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
717-
"CORE-V Immediate Branching");
710+
TRY_TO_DECODE_FEATURE_ANY(XCVFeatureGroup, DecoderTableXCV32,
711+
"CORE-V extensions");
718712
TRY_TO_DECODE_FEATURE_ANY(XqciFeatureGroup, DecoderTableXqci32,
719713
"Qualcomm uC Extensions");
720714

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13-
let DecoderNamespace = "XCVbitmanip" in {
13+
let DecoderNamespace = "XCV" in {
1414
class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
1515
string opcodestr, string argstr>
1616
: RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
@@ -54,7 +54,7 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32],
5454
def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
5555
(ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
5656
"cv.insert", "$rd, $rs1, $is3, $is2">;
57-
let DecoderNamespace = "XCVbitmanip" in
57+
let DecoderNamespace = "XCV" in
5858
def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
5959
(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
6060
"cv.insertr", "$rd, $rs1, $rs2">;
@@ -74,7 +74,7 @@ class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr>
7474
: RVInstR<funct7, funct3, OPC_CUSTOM_1,
7575
(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
7676
opcodestr, "$rd, $rs1, $rs2"> {
77-
let DecoderNamespace = "XCVmac";
77+
let DecoderNamespace = "XCV";
7878
}
7979

8080
class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
@@ -85,7 +85,7 @@ class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
8585

8686
let Inst{31-30} = funct2;
8787
let Inst{29-25} = imm5;
88-
let DecoderNamespace = "XCVmac";
88+
let DecoderNamespace = "XCV";
8989
}
9090

9191
class CVInstMacN<bits<2> funct2, bits<3> funct3, string opcodestr>
@@ -162,7 +162,7 @@ let Predicates = [HasVendorXCVmac, IsRV32] in {
162162
(CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
163163
} // Predicates = [HasVendorXCVmac, IsRV32]
164164

165-
let DecoderNamespace = "XCValu" in {
165+
let DecoderNamespace = "XCV" in {
166166
class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
167167
: RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
168168
(ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
@@ -197,7 +197,7 @@ let DecoderNamespace = "XCValu" in {
197197
let rs2 = 0b00000;
198198
}
199199

200-
} // DecoderNamespace = "XCValu"
200+
} // DecoderNamespace = "XCV"
201201

202202
let Predicates = [HasVendorXCValu, IsRV32],
203203
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
@@ -289,7 +289,7 @@ class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
289289
let Inst{31-27} = funct5;
290290
let Inst{26} = F;
291291
let Inst{25} = funct1;
292-
let DecoderNamespace = "XCVsimd";
292+
let DecoderNamespace = "XCV";
293293
}
294294

295295
class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
@@ -301,7 +301,7 @@ class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
301301
let Inst{26} = F;
302302
let Inst{25} = imm6{0}; // funct1 unused
303303
let Inst{24-20} = imm6{5-1};
304-
let DecoderNamespace = "XCVsimd";
304+
let DecoderNamespace = "XCV";
305305
}
306306

307307
class CVSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
@@ -497,7 +497,7 @@ class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
497497
: RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
498498
bits<5> imm5;
499499
let rs2 = imm5;
500-
let DecoderNamespace = "XCVbi";
500+
let DecoderNamespace = "XCV";
501501
}
502502

503503
let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
@@ -531,14 +531,14 @@ class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
531531
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
532532
opcodestr, "$rd, (${rs1}), ${imm12}"> {
533533
let Constraints = "$rs1_wb = $rs1";
534-
let DecoderNamespace = "XCVmem";
534+
let DecoderNamespace = "XCV";
535535
}
536536

537537
class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
538538
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
539539
opcodestr, "$rd, (${rs1}), ${rs2}"> {
540540
let Constraints = "$rs1_wb = $rs1";
541-
let DecoderNamespace = "XCVmem";
541+
let DecoderNamespace = "XCV";
542542
}
543543

544544
class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
@@ -552,7 +552,7 @@ class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
552552
let Inst{19-15} = cvrr{9-5};
553553
let Inst{14-12} = funct3;
554554
let Inst{11-7} = rd;
555-
let DecoderNamespace = "XCVmem";
555+
let DecoderNamespace = "XCV";
556556
}
557557

558558
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
@@ -587,7 +587,7 @@ class CVStore_ri_inc<bits<3> funct3, string opcodestr>
587587
(ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
588588
opcodestr, "$rs2, (${rs1}), ${imm12}"> {
589589
let Constraints = "$rs1_wb = $rs1";
590-
let DecoderNamespace = "XCVmem";
590+
let DecoderNamespace = "XCV";
591591
}
592592

593593
class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
@@ -603,7 +603,7 @@ class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
603603
let Inst{14-12} = funct3;
604604
let Inst{11-7} = rs3;
605605
let Inst{6-0} = OPC_CUSTOM_1.Value;
606-
let DecoderNamespace = "XCVmem";
606+
let DecoderNamespace = "XCV";
607607
}
608608

609609

@@ -619,7 +619,7 @@ class CVStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
619619
let Inst{14-12} = funct3;
620620
let Inst{11-7} = cvrr{4-0};
621621
let Inst{6-0} = OPC_CUSTOM_1.Value;
622-
let DecoderNamespace = "XCVmem";
622+
let DecoderNamespace = "XCV";
623623
}
624624

625625
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
@@ -656,7 +656,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
656656
"cv.sw", "$rs2, $cvrr">;
657657
}
658658

659-
let DecoderNamespace = "XCVelw" in
659+
let DecoderNamespace = "XCV" in
660660
class CVLoad_ri<bits<3> funct3, string opcodestr>
661661
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
662662
(ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;

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