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[SelectionDAG] Fold (avg x, 0) -> x >> 1
1 parent c0d03d2 commit 9b33320

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2 files changed

+7
-5
lines changed

2 files changed

+7
-5
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5083,7 +5083,11 @@ SDValue DAGCombiner::visitAVG(SDNode *N) {
50835083
if (N0 == N1 && Level >= AfterLegalizeTypes)
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return N0;
50855085

5086-
// TODO If we use avg for scalars anywhere, we can add (avgfl x, 0) -> x >> 1
5086+
if (isNullOrNullSplat(N1))
5087+
return DAG.getNode((Opcode == ISD::AVGFLOORS || Opcode == ISD::AVGCEILS)
5088+
? ISD::SRA
5089+
: ISD::SRL,
5090+
DL, VT, N0, DAG.getConstant(1, DL, VT));
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50885092
return SDValue();
50895093
}

llvm/test/CodeGen/AArch64/hadd-combine.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -464,8 +464,7 @@ define <8 x i16> @rhaddu_i_const_lhs(<8 x i16> %src1) {
464464
define <8 x i16> @rhaddu_i_const_zero(<8 x i16> %src1) {
465465
; CHECK-LABEL: rhaddu_i_const_zero:
466466
; CHECK: // %bb.0:
467-
; CHECK-NEXT: movi v1.2d, #0000000000000000
468-
; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
467+
; CHECK-NEXT: ushr v0.8h, v0.8h, #1
469468
; CHECK-NEXT: ret
470469
%result = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)
471470
ret <8 x i16> %result
@@ -633,8 +632,7 @@ define <8 x i16> @rhadds_i_const_lhs(<8 x i16> %src1) {
633632
define <8 x i16> @rhadds_i_const_zero(<8 x i16> %src1) {
634633
; CHECK-LABEL: rhadds_i_const_zero:
635634
; CHECK: // %bb.0:
636-
; CHECK-NEXT: movi v1.2d, #0000000000000000
637-
; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
635+
; CHECK-NEXT: sshr v0.8h, v0.8h, #1
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; CHECK-NEXT: ret
639637
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %src1)
640638
ret <8 x i16> %result

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