@@ -10976,28 +10976,28 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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// -> (logic_op (srl x, c1), (zext y))
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// c1 <= leadingzeros(zext(y))
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if (N1C && ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) {
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- SDValue lhs = N0.getOperand(0);
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- SDValue rhs = N0.getOperand(1);
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- SDValue shl ;
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- SDValue other ;
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- if (lhs .getOpcode() == ISD::SHL) {
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- shl = lhs ;
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- other = rhs ;
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- } else if (rhs .getOpcode() == ISD::SHL) {
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- shl = rhs ;
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- other = lhs ;
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- }
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- if (shl && shl .getOperand(1) == N1 && shl .hasOneUse()) {
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- SDValue zext = shl .getOperand(0);
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- if (zext .getOpcode() == ISD::ZERO_EXTEND) {
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- unsigned numLeadingZeros =
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- zext .getValueType().getScalarSizeInBits() -
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- zext .getOperand(0).getValueType().getScalarSizeInBits();
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- if (N1C->getZExtValue() <= numLeadingZeros ) {
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+ SDValue LHS = N0.getOperand(0);
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+ SDValue RHS = N0.getOperand(1);
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+ SDValue SHL ;
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+ SDValue Other ;
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+ if (LHS .getOpcode() == ISD::SHL) {
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+ SHL = LHS ;
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+ Other = RHS ;
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+ } else if (RHS .getOpcode() == ISD::SHL) {
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+ SHL = RHS ;
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+ Other = LHS ;
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+ }
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+ if (SHL && SHL .getOperand(1) == N1 && SHL .hasOneUse()) {
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+ SDValue ZExt = SHL .getOperand(0);
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+ if (ZExt .getOpcode() == ISD::ZERO_EXTEND) {
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+ unsigned NumLeadingZeros =
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+ ZExt .getValueType().getScalarSizeInBits() -
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+ ZExt .getOperand(0).getValueType().getScalarSizeInBits();
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+ if (N1C->getZExtValue() <= NumLeadingZeros ) {
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return DAG.getNode(
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N0.getOpcode(), SDLoc(N0), VT,
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- DAG.getNode(ISD::SRL, SDLoc(N0), VT, other , N1),
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- zext );
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+ DAG.getNode(ISD::SRL, SDLoc(N0), VT, Other , N1),
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+ ZExt );
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}
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}
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}
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