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[GISel] Handle more opcodes in constant_fold_binop (#102640)
Update the list of opcodes handled by the constant_fold_binop combine to match the ones that are folded in CSEMIRBuilder::buildInstr.
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+10
-21
lines changed

2 files changed

+10
-21
lines changed

llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1107,7 +1107,9 @@ def reassocs : GICombineGroup<[reassoc_ptradd, reassoc_comm_binops]>;
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// Constant fold operations.
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def constant_fold_binop : GICombineRule<
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(defs root:$d, apint_matchinfo:$matchinfo),
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(match (wip_match_opcode G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL, G_LSHR, G_ASHR):$d,
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(match (wip_match_opcode G_ADD, G_PTR_ADD, G_AND, G_ASHR, G_LSHR, G_MUL, G_OR,
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G_SHL, G_SUB, G_XOR, G_UDIV, G_SDIV, G_UREM, G_SREM,
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G_SMIN, G_SMAX, G_UMIN, G_UMAX):$d,
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[{ return Helper.matchConstantFoldBinOp(*${d}, ${matchinfo}); }]),
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(apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>;
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llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8,18 +8,9 @@ tracksRegLiveness: true
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body: |
99
bb.1:
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; CHECK-LABEL: name: test
11-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
12-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483647
13-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
14-
; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[C]], [[C1]]
15-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UMULH]], [[C2]](s32)
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; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[C]], [[C]]
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UREM]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LSHR]](s32)
19-
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s8)
20-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SEXT]]
21-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
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; CHECK-NEXT: $w0 = COPY [[TRUNC1]](s32)
11+
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
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; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s16) = G_CONSTANT i16 0
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%2:_(s1) = G_CONSTANT i1 true
@@ -49,14 +40,10 @@ tracksRegLiveness: true
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body: |
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bb.1:
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; CHECK-LABEL: name: test_inverted_div_rem
52-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[UDIVREM:%[0-9]+]]:_(s32), [[UDIVREM1:%[0-9]+]]:_ = G_UDIVREM [[C]], [[C]]
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UDIVREM]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UDIVREM1]](s32)
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; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s8)
57-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SEXT]]
58-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
59-
; CHECK-NEXT: $w0 = COPY [[TRUNC1]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
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; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s8)
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; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s16) = G_CONSTANT i16 0
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%2:_(s1) = G_CONSTANT i1 true

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