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Evandro Menezes
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[AArch64] Add the pipeline model for Exynos M5
Add the scheduling and cost models for Exynos M5.
1 parent 25f33d8 commit 9bdfee2

30 files changed

+3349
-35
lines changed

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -450,6 +450,7 @@ include "AArch64SchedFalkor.td"
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include "AArch64SchedKryo.td"
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include "AArch64SchedExynosM3.td"
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include "AArch64SchedExynosM4.td"
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include "AArch64SchedExynosM5.td"
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include "AArch64SchedThunderX.td"
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include "AArch64SchedThunderX2T99.td"
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@@ -790,7 +791,7 @@ def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
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def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
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def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
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def : ProcessorModel<"exynos-m5", ExynosM4Model, [ProcExynosM4]>;
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def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
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def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
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def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
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def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;

‎llvm/lib/Target/AArch64/AArch64SchedExynosM5.td

Lines changed: 1012 additions & 0 deletions
Large diffs are not rendered by default.

‎llvm/test/tools/llvm-mca/AArch64/Exynos/aes.s

Lines changed: 57 additions & 0 deletions
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@@ -0,0 +1,57 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
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aese v0.16b, v1.16b
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aesmc v0.16b, v0.16b
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9+
aesd v0.16b, v1.16b
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aesimc v0.16b, v0.16b
11+
12+
# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 400
14+
15+
# M3-NEXT: Total Cycles: 203
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# M4-NEXT: Total Cycles: 203
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# M5-NEXT: Total Cycles: 403
18+
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# ALL-NEXT: Total uOps: 400
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# ALL: Dispatch Width: 6
22+
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# M3-NEXT: uOps Per Cycle: 1.97
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# M3-NEXT: IPC: 1.97
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# M4-NEXT: uOps Per Cycle: 1.97
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# M4-NEXT: IPC: 1.97
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# M5-NEXT: uOps Per Cycle: 0.99
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# M5-NEXT: IPC: 0.99
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# ALL-NEXT: Block RThroughput: 2.0
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# M3-NEXT: 1 1 0.50 aese v0.16b, v1.16b
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# M3-NEXT: 1 1 0.50 aesmc v0.16b, v0.16b
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# M3-NEXT: 1 1 0.50 aesd v0.16b, v1.16b
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# M3-NEXT: 1 1 0.50 aesimc v0.16b, v0.16b
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# M4-NEXT: 1 1 0.50 aese v0.16b, v1.16b
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# M4-NEXT: 1 1 0.50 aesmc v0.16b, v0.16b
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# M4-NEXT: 1 1 0.50 aesd v0.16b, v1.16b
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# M4-NEXT: 1 1 0.50 aesimc v0.16b, v0.16b
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# M5-NEXT: 1 2 0.50 aese v0.16b, v1.16b
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# M5-NEXT: 1 2 0.50 aesmc v0.16b, v0.16b
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# M5-NEXT: 1 2 0.50 aesd v0.16b, v1.16b
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# M5-NEXT: 1 2 0.50 aesimc v0.16b, v0.16b

‎llvm/test/tools/llvm-mca/AArch64/Exynos/asimd-ld1.s

Lines changed: 189 additions & 0 deletions
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
5+
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ld1 {v0.s}[0], [sp]
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ld1r {v0.2s}, [sp]
8+
ld1 {v0.2s}, [sp]
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ld1 {v0.2s, v1.2s}, [sp]
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ld1 {v0.2s, v1.2s, v2.2s}, [sp]
11+
ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
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13+
ld1 {v0.d}[0], [sp]
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ld1r {v0.2d}, [sp]
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ld1 {v0.2d}, [sp]
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ld1 {v0.2d, v1.2d}, [sp]
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ld1 {v0.2d, v1.2d, v2.2d}, [sp]
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ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
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ld1 {v0.s}[0], [sp], #4
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ld1r {v0.2s}, [sp], #4
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ld1 {v0.2s}, [sp], #8
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ld1 {v0.2s, v1.2s}, [sp], #16
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ld1 {v0.2s, v1.2s, v2.2s}, [sp], #24
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ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #32
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ld1 {v0.d}[0], [sp], #8
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ld1r {v0.2d}, [sp], #8
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ld1 {v0.2d}, [sp], #16
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ld1 {v0.2d, v1.2d}, [sp], #32
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ld1 {v0.2d, v1.2d, v2.2d}, [sp], #48
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ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64
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ld1 {v0.s}[0], [sp], x0
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ld1r {v0.2s}, [sp], x0
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ld1 {v0.2s}, [sp], x0
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ld1 {v0.2s, v1.2s}, [sp], x0
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ld1 {v0.2s, v1.2s, v2.2s}, [sp], x0
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ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0
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41+
ld1 {v0.d}[0], [sp], x0
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ld1r {v0.2d}, [sp], x0
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ld1 {v0.2d}, [sp], x0
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ld1 {v0.2d, v1.2d}, [sp], x0
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ld1 {v0.2d, v1.2d, v2.2d}, [sp], x0
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ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x0
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48+
# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 3600
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51+
# M3-NEXT: Total Cycles: 14903
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# M4-NEXT: Total Cycles: 14703
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# M5-NEXT: Total Cycles: 17203
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55+
# ALL-NEXT: Total uOps: 10200
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57+
# ALL: Dispatch Width: 6
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# M3-NEXT: uOps Per Cycle: 0.68
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# M3-NEXT: IPC: 0.24
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# M4-NEXT: uOps Per Cycle: 0.69
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# M4-NEXT: IPC: 0.24
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# M5-NEXT: uOps Per Cycle: 0.59
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# M5-NEXT: IPC: 0.21
67+
68+
# ALL-NEXT: Block RThroughput: 39.0
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70+
# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# M3-NEXT: 2 7 1.00 * ld1 { v0.s }[0], [sp]
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# M3-NEXT: 1 5 0.50 * ld1r { v0.2s }, [sp]
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# M3-NEXT: 1 5 0.50 * ld1 { v0.2s }, [sp]
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# M3-NEXT: 2 5 1.00 * ld1 { v0.2s, v1.2s }, [sp]
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# M3-NEXT: 3 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp]
85+
# M3-NEXT: 4 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
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# M3-NEXT: 2 6 1.00 * ld1 { v0.d }[0], [sp]
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# M3-NEXT: 1 5 0.50 * ld1r { v0.2d }, [sp]
88+
# M3-NEXT: 1 5 0.50 * ld1 { v0.2d }, [sp]
89+
# M3-NEXT: 2 5 1.00 * ld1 { v0.2d, v1.2d }, [sp]
90+
# M3-NEXT: 3 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp]
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# M3-NEXT: 4 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
92+
# M3-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], #4
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# M3-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], #4
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# M3-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], #8
95+
# M3-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], #16
96+
# M3-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], #24
97+
# M3-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
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# M3-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], #8
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# M3-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], #8
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# M3-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], #16
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# M3-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], #32
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# M3-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], #48
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# M3-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
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# M3-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], x0
105+
# M3-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], x0
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# M3-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], x0
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# M3-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], x0
108+
# M3-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], x0
109+
# M3-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
110+
# M3-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], x0
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# M3-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], x0
112+
# M3-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], x0
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# M3-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], x0
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# M3-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], x0
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# M3-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
116+
117+
# M4-NEXT: 2 6 1.00 * ld1 { v0.s }[0], [sp]
118+
# M4-NEXT: 1 5 0.50 * ld1r { v0.2s }, [sp]
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# M4-NEXT: 1 5 0.50 * ld1 { v0.2s }, [sp]
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# M4-NEXT: 2 5 1.00 * ld1 { v0.2s, v1.2s }, [sp]
121+
# M4-NEXT: 3 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp]
122+
# M4-NEXT: 4 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
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# M4-NEXT: 2 6 1.00 * ld1 { v0.d }[0], [sp]
124+
# M4-NEXT: 1 5 0.50 * ld1r { v0.2d }, [sp]
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# M4-NEXT: 1 5 0.50 * ld1 { v0.2d }, [sp]
126+
# M4-NEXT: 2 5 1.00 * ld1 { v0.2d, v1.2d }, [sp]
127+
# M4-NEXT: 3 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp]
128+
# M4-NEXT: 4 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
129+
# M4-NEXT: 3 6 1.00 * ld1 { v0.s }[0], [sp], #4
130+
# M4-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], #4
131+
# M4-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], #8
132+
# M4-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], #16
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# M4-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], #24
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# M4-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
135+
# M4-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], #8
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# M4-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], #8
137+
# M4-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], #16
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# M4-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], #32
139+
# M4-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], #48
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# M4-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
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# M4-NEXT: 3 6 1.00 * ld1 { v0.s }[0], [sp], x0
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# M4-NEXT: 2 5 0.50 * ld1r { v0.2s }, [sp], x0
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# M4-NEXT: 2 5 0.50 * ld1 { v0.2s }, [sp], x0
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# M4-NEXT: 3 5 1.00 * ld1 { v0.2s, v1.2s }, [sp], x0
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# M4-NEXT: 4 6 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], x0
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# M4-NEXT: 5 6 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
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# M4-NEXT: 3 6 1.00 * ld1 { v0.d }[0], [sp], x0
148+
# M4-NEXT: 2 5 0.50 * ld1r { v0.2d }, [sp], x0
149+
# M4-NEXT: 2 5 0.50 * ld1 { v0.2d }, [sp], x0
150+
# M4-NEXT: 3 5 1.00 * ld1 { v0.2d, v1.2d }, [sp], x0
151+
# M4-NEXT: 4 6 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], x0
152+
# M4-NEXT: 5 6 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0
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154+
# M5-NEXT: 2 7 1.00 * ld1 { v0.s }[0], [sp]
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# M5-NEXT: 1 6 0.50 * ld1r { v0.2s }, [sp]
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# M5-NEXT: 1 6 0.50 * ld1 { v0.2s }, [sp]
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# M5-NEXT: 2 6 1.00 * ld1 { v0.2s, v1.2s }, [sp]
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# M5-NEXT: 3 7 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp]
159+
# M5-NEXT: 4 7 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp]
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# M5-NEXT: 2 7 1.00 * ld1 { v0.d }[0], [sp]
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# M5-NEXT: 1 6 0.50 * ld1r { v0.2d }, [sp]
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# M5-NEXT: 1 6 0.50 * ld1 { v0.2d }, [sp]
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# M5-NEXT: 2 6 1.00 * ld1 { v0.2d, v1.2d }, [sp]
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# M5-NEXT: 3 7 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp]
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# M5-NEXT: 4 7 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp]
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# M5-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], #4
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# M5-NEXT: 2 6 0.50 * ld1r { v0.2s }, [sp], #4
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# M5-NEXT: 2 6 0.50 * ld1 { v0.2s }, [sp], #8
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# M5-NEXT: 3 6 1.00 * ld1 { v0.2s, v1.2s }, [sp], #16
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# M5-NEXT: 4 7 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], #24
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# M5-NEXT: 5 7 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #32
172+
# M5-NEXT: 3 7 1.00 * ld1 { v0.d }[0], [sp], #8
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# M5-NEXT: 2 6 0.50 * ld1r { v0.2d }, [sp], #8
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# M5-NEXT: 2 6 0.50 * ld1 { v0.2d }, [sp], #16
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# M5-NEXT: 3 6 1.00 * ld1 { v0.2d, v1.2d }, [sp], #32
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# M5-NEXT: 4 7 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], #48
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# M5-NEXT: 5 7 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], #64
178+
# M5-NEXT: 3 7 1.00 * ld1 { v0.s }[0], [sp], x0
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# M5-NEXT: 2 6 0.50 * ld1r { v0.2s }, [sp], x0
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# M5-NEXT: 2 6 0.50 * ld1 { v0.2s }, [sp], x0
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# M5-NEXT: 3 6 1.00 * ld1 { v0.2s, v1.2s }, [sp], x0
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# M5-NEXT: 4 7 1.50 * ld1 { v0.2s, v1.2s, v2.2s }, [sp], x0
183+
# M5-NEXT: 5 7 2.00 * ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x0
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# M5-NEXT: 3 7 1.00 * ld1 { v0.d }[0], [sp], x0
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# M5-NEXT: 2 6 0.50 * ld1r { v0.2d }, [sp], x0
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# M5-NEXT: 2 6 0.50 * ld1 { v0.2d }, [sp], x0
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# M5-NEXT: 3 6 1.00 * ld1 { v0.2d, v1.2d }, [sp], x0
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# M5-NEXT: 4 7 1.50 * ld1 { v0.2d, v1.2d, v2.2d }, [sp], x0
189+
# M5-NEXT: 5 7 2.00 * ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [sp], x0

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