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[RISCV][GISel] Add RISCVPassConfig::getCSEConfig() to match other targets. (#110755)
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71 files changed

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‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "TargetInfo/RISCVTargetInfo.h"
2020
#include "llvm/ADT/STLExtras.h"
2121
#include "llvm/Analysis/TargetTransformInfo.h"
22+
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
2223
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
2324
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
2425
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
@@ -374,13 +375,19 @@ class RISCVPassConfig : public TargetPassConfig {
374375
void addPreRegAlloc() override;
375376
void addPostRegAlloc() override;
376377
void addFastRegAlloc() override;
378+
379+
std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
377380
};
378381
} // namespace
379382

380383
TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
381384
return new RISCVPassConfig(*this, PM);
382385
}
383386

387+
std::unique_ptr<CSEConfigBase> RISCVPassConfig::getCSEConfig() const {
388+
return getStandardCSEConfigForOpt(TM->getOptLevel());
389+
}
390+
384391
FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
385392
// Initialize the global default.
386393
llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,

‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-half.ll

Lines changed: 76 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -870,31 +870,31 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
870870
; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2
871871
; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
872872
; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
873-
; RV32I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
874-
; RV32I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
875-
; RV32I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
876-
; RV32I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
877-
; RV32I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
878-
; RV32I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
879-
; RV32I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
880-
; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
873+
; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
874+
; RV32I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
875+
; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
876+
; RV32I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
877+
; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
878+
; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
879+
; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
880+
; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(p0) = COPY $x2
881881
; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
882-
; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s32)
883-
; RV32I-NEXT: G_STORE [[ANYEXT8]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
882+
; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY7]], [[C2]](s32)
883+
; RV32I-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
884884
; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
885885
; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32)
886-
; RV32I-NEXT: $x12 = COPY [[ANYEXT2]](s32)
887-
; RV32I-NEXT: $x13 = COPY [[ANYEXT3]](s32)
888-
; RV32I-NEXT: $x14 = COPY [[ANYEXT4]](s32)
889-
; RV32I-NEXT: $x15 = COPY [[ANYEXT5]](s32)
890-
; RV32I-NEXT: $x16 = COPY [[ANYEXT6]](s32)
891-
; RV32I-NEXT: $x17 = COPY [[ANYEXT7]](s32)
886+
; RV32I-NEXT: $x12 = COPY [[COPY2]](s32)
887+
; RV32I-NEXT: $x13 = COPY [[ANYEXT2]](s32)
888+
; RV32I-NEXT: $x14 = COPY [[COPY3]](s32)
889+
; RV32I-NEXT: $x15 = COPY [[ANYEXT3]](s32)
890+
; RV32I-NEXT: $x16 = COPY [[COPY4]](s32)
891+
; RV32I-NEXT: $x17 = COPY [[COPY5]](s32)
892892
; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
893893
; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2
894-
; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
895-
; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
896-
; RV32I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
897-
; RV32I-NEXT: $x10 = COPY [[ANYEXT9]](s32)
894+
; RV32I-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
895+
; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
896+
; RV32I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
897+
; RV32I-NEXT: $x10 = COPY [[ANYEXT4]](s32)
898898
; RV32I-NEXT: PseudoRET implicit $x10
899899
;
900900
; RV32IF-LABEL: name: caller_half_return_stack2
@@ -910,28 +910,28 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
910910
; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
911911
; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
912912
; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
913-
; RV32IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
914-
; RV32IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
915-
; RV32IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
916-
; RV32IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
917-
; RV32IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
918-
; RV32IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
919-
; RV32IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
913+
; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
914+
; RV32IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
915+
; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
916+
; RV32IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
917+
; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
918+
; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
919+
; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
920920
; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
921921
; RV32IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32)
922-
; RV32IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32)
923-
; RV32IF-NEXT: $f13_f = COPY [[ANYEXT3]](s32)
924-
; RV32IF-NEXT: $f14_f = COPY [[ANYEXT4]](s32)
925-
; RV32IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32)
926-
; RV32IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32)
927-
; RV32IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32)
928-
; RV32IF-NEXT: $x10 = COPY [[ANYEXT8]](s32)
922+
; RV32IF-NEXT: $f12_f = COPY [[COPY2]](s32)
923+
; RV32IF-NEXT: $f13_f = COPY [[ANYEXT2]](s32)
924+
; RV32IF-NEXT: $f14_f = COPY [[COPY3]](s32)
925+
; RV32IF-NEXT: $f15_f = COPY [[ANYEXT3]](s32)
926+
; RV32IF-NEXT: $f16_f = COPY [[COPY4]](s32)
927+
; RV32IF-NEXT: $f17_f = COPY [[COPY5]](s32)
928+
; RV32IF-NEXT: $x10 = COPY [[COPY6]](s32)
929929
; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f
930930
; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
931-
; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
932-
; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
933-
; RV32IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
934-
; RV32IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32)
931+
; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f10_f
932+
; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32)
933+
; RV32IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
934+
; RV32IF-NEXT: $f10_f = COPY [[ANYEXT4]](s32)
935935
; RV32IF-NEXT: PseudoRET implicit $f10_f
936936
;
937937
; RV32IZFH-LABEL: name: caller_half_return_stack2
@@ -972,31 +972,31 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
972972
; RV64I-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
973973
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
974974
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s16)
975-
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
976-
; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
977-
; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
978-
; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
979-
; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
980-
; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
981-
; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
982-
; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
975+
; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64)
976+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
977+
; RV64I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64)
978+
; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
979+
; RV64I-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY [[ANYEXT3]](s64)
980+
; RV64I-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ANYEXT3]](s64)
981+
; RV64I-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64)
982+
; RV64I-NEXT: [[COPY7:%[0-9]+]]:_(p0) = COPY $x2
983983
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
984-
; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
985-
; RV64I-NEXT: G_STORE [[ANYEXT8]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
984+
; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY7]], [[C2]](s64)
985+
; RV64I-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
986986
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
987987
; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
988-
; RV64I-NEXT: $x12 = COPY [[ANYEXT2]](s64)
989-
; RV64I-NEXT: $x13 = COPY [[ANYEXT3]](s64)
990-
; RV64I-NEXT: $x14 = COPY [[ANYEXT4]](s64)
991-
; RV64I-NEXT: $x15 = COPY [[ANYEXT5]](s64)
992-
; RV64I-NEXT: $x16 = COPY [[ANYEXT6]](s64)
993-
; RV64I-NEXT: $x17 = COPY [[ANYEXT7]](s64)
988+
; RV64I-NEXT: $x12 = COPY [[COPY2]](s64)
989+
; RV64I-NEXT: $x13 = COPY [[ANYEXT2]](s64)
990+
; RV64I-NEXT: $x14 = COPY [[COPY3]](s64)
991+
; RV64I-NEXT: $x15 = COPY [[ANYEXT3]](s64)
992+
; RV64I-NEXT: $x16 = COPY [[COPY4]](s64)
993+
; RV64I-NEXT: $x17 = COPY [[COPY5]](s64)
994994
; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
995995
; RV64I-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2
996-
; RV64I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
997-
; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s64)
998-
; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s16)
999-
; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64)
996+
; RV64I-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
997+
; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s64)
998+
; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s16)
999+
; RV64I-NEXT: $x10 = COPY [[ANYEXT4]](s64)
10001000
; RV64I-NEXT: PseudoRET implicit $x10
10011001
;
10021002
; RV64IF-LABEL: name: caller_half_return_stack2
@@ -1012,28 +1012,28 @@ define half @caller_half_return_stack2(half %x, half %y) nounwind {
10121012
; RV64IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
10131013
; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
10141014
; RV64IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
1015-
; RV64IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
1016-
; RV64IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
1017-
; RV64IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
1018-
; RV64IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1019-
; RV64IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1020-
; RV64IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1015+
; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
1016+
; RV64IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
1017+
; RV64IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
1018+
; RV64IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1019+
; RV64IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
1020+
; RV64IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
10211021
; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
10221022
; RV64IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32)
1023-
; RV64IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32)
1024-
; RV64IF-NEXT: $f13_f = COPY [[ANYEXT3]](s32)
1025-
; RV64IF-NEXT: $f14_f = COPY [[ANYEXT4]](s32)
1026-
; RV64IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32)
1027-
; RV64IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32)
1028-
; RV64IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32)
1029-
; RV64IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
1030-
; RV64IF-NEXT: $x10 = COPY [[ANYEXT8]](s64)
1023+
; RV64IF-NEXT: $f12_f = COPY [[COPY2]](s32)
1024+
; RV64IF-NEXT: $f13_f = COPY [[ANYEXT2]](s32)
1025+
; RV64IF-NEXT: $f14_f = COPY [[COPY3]](s32)
1026+
; RV64IF-NEXT: $f15_f = COPY [[ANYEXT3]](s32)
1027+
; RV64IF-NEXT: $f16_f = COPY [[COPY4]](s32)
1028+
; RV64IF-NEXT: $f17_f = COPY [[COPY5]](s32)
1029+
; RV64IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
1030+
; RV64IF-NEXT: $x10 = COPY [[ANYEXT4]](s64)
10311031
; RV64IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f
10321032
; RV64IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
1033-
; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
1034-
; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
1035-
; RV64IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
1036-
; RV64IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32)
1033+
; RV64IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f10_f
1034+
; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
1035+
; RV64IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
1036+
; RV64IF-NEXT: $f10_f = COPY [[ANYEXT5]](s32)
10371037
; RV64IF-NEXT: PseudoRET implicit $f10_f
10381038
;
10391039
; RV64IZFH-LABEL: name: caller_half_return_stack2

‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1091,8 +1091,8 @@ define %struct.large2 @callee_large_struct_ret2() nounwind {
10911091
; RV32I-NEXT: {{ $}}
10921092
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
10931093
; RV32I-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1094-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1095-
; RV32I-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
1094+
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
1095+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
10961096
; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10971097
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
10981098
; RV32I-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3

‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -747,7 +747,7 @@ define %struct.large2 @callee_large_struct_ret2() nounwind {
747747
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
748748
; RV64I-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
749749
; RV64I-NEXT: [[DEF1:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
750-
; RV64I-NEXT: [[DEF2:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
750+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
751751
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
752752
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 2
753753
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 3.000000e+00

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -110,16 +110,14 @@ body: |
110110
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
111111
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
112112
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32)
113-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
114-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C1]](s32)
115113
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
116114
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[ASHR]]
117115
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
118-
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR1]]
116+
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR]]
119117
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
120118
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
121119
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[ASHR]]
122-
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[ASHR1]]
120+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[ASHR]]
123121
; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
124122
; CHECK-NEXT: $x11 = COPY [[XOR1]](s32)
125123
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,16 +14,15 @@ body: |
1414
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
1515
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
1616
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
17-
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
18-
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
19-
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
20-
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C2]](s64)
21-
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
22-
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC1]], [[ASHR1]]
17+
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s64)
18+
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
19+
; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C1]](s64)
20+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
21+
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR1]]
2322
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
2423
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
25-
; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
26-
; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]
24+
; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
25+
; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
2726
; RV64I-NEXT: $x10 = COPY [[AND]](s64)
2827
; RV64I-NEXT: PseudoRET implicit $x10
2928
;
@@ -56,8 +55,8 @@ body: |
5655
; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
5756
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
5857
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s64)
59-
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
60-
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC1]], [[ASHR]]
58+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
59+
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR]]
6160
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
6261
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
6362
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48

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