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[RISCV] Support vwsll in combineBinOp_VLToVWBinOp_VL (#87620)
If the subtarget has +zvbb then we can attempt folding shl and shl_vl to vwsll nodes. There are few test cases where we still don't pick up the vwsll: - For fixed vector vwsll.vi on RV32, see the FIXME for VMV_V_X_VL in fillUpExtensionSupport for support implicit sign extension - For scalable vector vwsll.vi we need to support ISD::SPLAT_VECTOR, see #87249
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3 files changed

+77
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 37 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -13543,6 +13543,7 @@ enum ExtKind : uint8_t { ZExt = 1 << 0, SExt = 1 << 1, FPExt = 1 << 2 };
1354313543
/// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w
1354413544
/// sub | sub_vl -> vwsub(u) | vwsub(u)_w
1354513545
/// mul | mul_vl -> vwmul(u) | vwmul_su
13546+
/// shl | shl_vl -> vwsll
1354613547
/// fadd -> vfwadd | vfwadd_w
1354713548
/// fsub -> vfwsub | vfwsub_w
1354813549
/// fmul -> vfwmul
@@ -13712,6 +13713,9 @@ struct NodeExtensionHelper {
1371213713
case ISD::MUL:
1371313714
case RISCVISD::MUL_VL:
1371413715
return RISCVISD::VWMULU_VL;
13716+
case ISD::SHL:
13717+
case RISCVISD::SHL_VL:
13718+
return RISCVISD::VWSLL_VL;
1371513719
default:
1371613720
llvm_unreachable("Unexpected opcode");
1371713721
}
@@ -13853,7 +13857,8 @@ struct NodeExtensionHelper {
1385313857
}
1385413858

1385513859
/// Check if \p Root supports any extension folding combines.
13856-
static bool isSupportedRoot(const SDNode *Root) {
13860+
static bool isSupportedRoot(const SDNode *Root,
13861+
const RISCVSubtarget &Subtarget) {
1385713862
switch (Root->getOpcode()) {
1385813863
case ISD::ADD:
1385913864
case ISD::SUB:
@@ -13879,6 +13884,11 @@ struct NodeExtensionHelper {
1387913884
case RISCVISD::VFWADD_W_VL:
1388013885
case RISCVISD::VFWSUB_W_VL:
1388113886
return true;
13887+
case ISD::SHL:
13888+
return Root->getValueType(0).isScalableVector() &&
13889+
Subtarget.hasStdExtZvbb();
13890+
case RISCVISD::SHL_VL:
13891+
return Subtarget.hasStdExtZvbb();
1388213892
default:
1388313893
return false;
1388413894
}
@@ -13887,8 +13897,9 @@ struct NodeExtensionHelper {
1388713897
/// Build a NodeExtensionHelper for \p Root.getOperand(\p OperandIdx).
1388813898
NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG,
1388913899
const RISCVSubtarget &Subtarget) {
13890-
assert(isSupportedRoot(Root) && "Trying to build an helper with an "
13891-
"unsupported root");
13900+
assert(isSupportedRoot(Root, Subtarget) &&
13901+
"Trying to build an helper with an "
13902+
"unsupported root");
1389213903
assert(OperandIdx < 2 && "Requesting something else than LHS or RHS");
1389313904
assert(DAG.getTargetLoweringInfo().isTypeLegal(Root->getValueType(0)));
1389413905
OrigOperand = Root->getOperand(OperandIdx);
@@ -13928,12 +13939,13 @@ struct NodeExtensionHelper {
1392813939
static std::pair<SDValue, SDValue>
1392913940
getMaskAndVL(const SDNode *Root, SelectionDAG &DAG,
1393013941
const RISCVSubtarget &Subtarget) {
13931-
assert(isSupportedRoot(Root) && "Unexpected root");
13942+
assert(isSupportedRoot(Root, Subtarget) && "Unexpected root");
1393213943
switch (Root->getOpcode()) {
1393313944
case ISD::ADD:
1393413945
case ISD::SUB:
1393513946
case ISD::MUL:
13936-
case ISD::OR: {
13947+
case ISD::OR:
13948+
case ISD::SHL: {
1393713949
SDLoc DL(Root);
1393813950
MVT VT = Root->getSimpleValueType(0);
1393913951
return getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
@@ -13964,6 +13976,8 @@ struct NodeExtensionHelper {
1396413976
case RISCVISD::VWSUBU_W_VL:
1396513977
case RISCVISD::FSUB_VL:
1396613978
case RISCVISD::VFWSUB_W_VL:
13979+
case ISD::SHL:
13980+
case RISCVISD::SHL_VL:
1396713981
return false;
1396813982
default:
1396913983
llvm_unreachable("Unexpected opcode");
@@ -14017,6 +14031,7 @@ struct CombineResult {
1401714031
case ISD::SUB:
1401814032
case ISD::MUL:
1401914033
case ISD::OR:
14034+
case ISD::SHL:
1402014035
Merge = DAG.getUNDEF(Root->getValueType(0));
1402114036
break;
1402214037
}
@@ -14178,6 +14193,11 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
1417814193
// mul -> vwmulsu
1417914194
Strategies.push_back(canFoldToVW_SU);
1418014195
break;
14196+
case ISD::SHL:
14197+
case RISCVISD::SHL_VL:
14198+
// shl -> vwsll
14199+
Strategies.push_back(canFoldToVWWithZEXT);
14200+
break;
1418114201
case RISCVISD::VWADD_W_VL:
1418214202
case RISCVISD::VWSUB_W_VL:
1418314203
// vwadd_w|vwsub_w -> vwadd|vwsub
@@ -14205,6 +14225,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
1420514225
/// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w
1420614226
/// sub | sub_vl -> vwsub(u) | vwsub(u)_w
1420714227
/// mul | mul_vl -> vwmul(u) | vwmul_su
14228+
/// shl | shl_vl -> vwsll
1420814229
/// fadd_vl -> vfwadd | vfwadd_w
1420914230
/// fsub_vl -> vfwsub | vfwsub_w
1421014231
/// fmul_vl -> vfwmul
@@ -14219,7 +14240,7 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
1421914240
if (DCI.isBeforeLegalize())
1422014241
return SDValue();
1422114242

14222-
if (!NodeExtensionHelper::isSupportedRoot(N))
14243+
if (!NodeExtensionHelper::isSupportedRoot(N, Subtarget))
1422314244
return SDValue();
1422414245

1422514246
SmallVector<SDNode *> Worklist;
@@ -14230,7 +14251,7 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
1423014251

1423114252
while (!Worklist.empty()) {
1423214253
SDNode *Root = Worklist.pop_back_val();
14233-
if (!NodeExtensionHelper::isSupportedRoot(Root))
14254+
if (!NodeExtensionHelper::isSupportedRoot(Root, Subtarget))
1423414255
return SDValue();
1423514256

1423614257
NodeExtensionHelper LHS(N, 0, DAG, Subtarget);
@@ -16325,9 +16346,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1632516346
VPSN->getMemOperand(), IndexType);
1632616347
break;
1632716348
}
16349+
case RISCVISD::SHL_VL:
16350+
if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget))
16351+
return V;
16352+
[[fallthrough]];
1632816353
case RISCVISD::SRA_VL:
16329-
case RISCVISD::SRL_VL:
16330-
case RISCVISD::SHL_VL: {
16354+
case RISCVISD::SRL_VL: {
1633116355
SDValue ShAmt = N->getOperand(1);
1633216356
if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
1633316357
// We don't need the upper 32 bits of a 64-bit element for a shift amount.
@@ -16347,6 +16371,10 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1634716371
[[fallthrough]];
1634816372
case ISD::SRL:
1634916373
case ISD::SHL: {
16374+
if (N->getOpcode() == ISD::SHL) {
16375+
if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget))
16376+
return V;
16377+
}
1635016378
SDValue ShAmt = N->getOperand(1);
1635116379
if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
1635216380
// We don't need the upper 32 bits of a 64-bit element for a shift amount.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll

Lines changed: 28 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -111,8 +111,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) {
111111
; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_zext:
112112
; CHECK-ZVBB: # %bb.0:
113113
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
114-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
115-
; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9
114+
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
116115
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
117116
; CHECK-ZVBB-NEXT: ret
118117
%head = insertelement <4 x i32> poison, i32 %b, i32 0
@@ -371,8 +370,7 @@ define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) {
371370
; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_zext:
372371
; CHECK-ZVBB: # %bb.0:
373372
; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
374-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
375-
; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9
373+
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
376374
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
377375
; CHECK-ZVBB-NEXT: ret
378376
%head = insertelement <8 x i16> poison, i16 %b, i32 0
@@ -642,8 +640,7 @@ define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) {
642640
; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_zext:
643641
; CHECK-ZVBB: # %bb.0:
644642
; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
645-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
646-
; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9
643+
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
647644
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
648645
; CHECK-ZVBB-NEXT: ret
649646
%head = insertelement <16 x i8> poison, i8 %b, i32 0
@@ -710,10 +707,10 @@ define <4 x i64> @vwsll_vv_v4i64_v4i8_zext(<4 x i8> %a, <4 x i8> %b) {
710707
;
711708
; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_zext:
712709
; CHECK-ZVBB: # %bb.0:
713-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
714-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
715-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
716-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
710+
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
711+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
712+
; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9
713+
; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11
717714
; CHECK-ZVBB-NEXT: ret
718715
%x = zext <4 x i8> %a to <4 x i64>
719716
%y = zext <4 x i8> %b to <4 x i64>
@@ -784,11 +781,8 @@ define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_zext(<4 x i8> %a, i32 %b) {
784781
; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_zext:
785782
; CHECK-ZVBB: # %bb.0:
786783
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
787-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
788-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
789-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
790-
; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9
791-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
784+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
785+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
792786
; CHECK-ZVBB-NEXT: ret
793787
%head = insertelement <4 x i32> poison, i32 %b, i32 0
794788
%splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
@@ -839,12 +833,9 @@ define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_zext(<4 x i8> %a, i16 %b) {
839833
;
840834
; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_zext:
841835
; CHECK-ZVBB: # %bb.0:
842-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
843-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
844-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
845-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
846-
; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9
847-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
836+
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
837+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
838+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
848839
; CHECK-ZVBB-NEXT: ret
849840
%head = insertelement <4 x i16> poison, i16 %b, i32 0
850841
%splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer
@@ -895,12 +886,9 @@ define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_zext(<4 x i8> %a, i8 %b) {
895886
;
896887
; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_zext:
897888
; CHECK-ZVBB: # %bb.0:
898-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
899-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
900-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
901-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
902-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
903-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
889+
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
890+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
891+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
904892
; CHECK-ZVBB-NEXT: ret
905893
%head = insertelement <4 x i8> poison, i8 %b, i32 0
906894
%splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -918,12 +906,19 @@ define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) {
918906
; CHECK-NEXT: vsll.vi v8, v10, 2
919907
; CHECK-NEXT: ret
920908
;
921-
; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8:
922-
; CHECK-ZVBB: # %bb.0:
923-
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
924-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
925-
; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2
926-
; CHECK-ZVBB-NEXT: ret
909+
; CHECK-ZVBB-RV32-LABEL: vwsll_vi_v4i64_v4i8:
910+
; CHECK-ZVBB-RV32: # %bb.0:
911+
; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
912+
; CHECK-ZVBB-RV32-NEXT: vzext.vf8 v10, v8
913+
; CHECK-ZVBB-RV32-NEXT: vsll.vi v8, v10, 2
914+
; CHECK-ZVBB-RV32-NEXT: ret
915+
;
916+
; CHECK-ZVBB-RV64-LABEL: vwsll_vi_v4i64_v4i8:
917+
; CHECK-ZVBB-RV64: # %bb.0:
918+
; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
919+
; CHECK-ZVBB-RV64-NEXT: vzext.vf4 v10, v8
920+
; CHECK-ZVBB-RV64-NEXT: vwsll.vi v8, v10, 2
921+
; CHECK-ZVBB-RV64-NEXT: ret
927922
%x = zext <4 x i8> %a to <4 x i64>
928923
%z = shl <4 x i64> %x, splat (i64 2)
929924
ret <4 x i64> %z

‎llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

Lines changed: 12 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -665,10 +665,10 @@ define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <v
665665
;
666666
; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
667667
; CHECK-ZVBB: # %bb.0:
668-
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
669-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
670-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
671-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
668+
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
669+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
670+
; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9
671+
; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11
672672
; CHECK-ZVBB-NEXT: ret
673673
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
674674
%y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>
@@ -739,11 +739,8 @@ define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a
739739
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
740740
; CHECK-ZVBB: # %bb.0:
741741
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
742-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
743-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
744-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
745-
; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9
746-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
742+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
743+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
747744
; CHECK-ZVBB-NEXT: ret
748745
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
749746
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -794,12 +791,9 @@ define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a
794791
;
795792
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
796793
; CHECK-ZVBB: # %bb.0:
797-
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
798-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
799-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
800-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
801-
; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9
802-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
794+
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
795+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
796+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
803797
; CHECK-ZVBB-NEXT: ret
804798
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
805799
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -850,12 +844,9 @@ define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a,
850844
;
851845
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
852846
; CHECK-ZVBB: # %bb.0:
853-
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
854-
; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
855-
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
856-
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
857-
; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
858-
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
847+
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
848+
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
849+
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
859850
; CHECK-ZVBB-NEXT: ret
860851
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
861852
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer

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