Skip to content

Commit 9ceb45c

Browse files
LukacmaLukacma
authored
[AArch64][SVE] optimisation for unary SVE store intrinsics with no active lanes (#95793)
This patch extends #73964 and adds optimisation of store SVE intrinsics when predicate is zero.
1 parent d7da0ae commit 9ceb45c

File tree

2 files changed

+346
-0
lines changed

2 files changed

+346
-0
lines changed

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -985,6 +985,16 @@ static bool isAllActivePredicate(Value *Pred) {
985985
m_ConstantInt<AArch64SVEPredPattern::all>()));
986986
}
987987

988+
// Erase unary operation where predicate has all inactive lanes
989+
static std::optional<Instruction *>
990+
instCombineSVENoActiveUnaryErase(InstCombiner &IC, IntrinsicInst &II,
991+
int PredPos) {
992+
if (match(II.getOperand(PredPos), m_ZeroInt())) {
993+
return IC.eraseInstFromFunction(II);
994+
}
995+
return std::nullopt;
996+
}
997+
988998
// Simplify unary operation where predicate has all inactive lanes by replacing
989999
// instruction with zeroed object
9901000
static std::optional<Instruction *>
@@ -2007,6 +2017,32 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
20072017
default:
20082018
break;
20092019

2020+
case Intrinsic::aarch64_sve_st1_scatter:
2021+
case Intrinsic::aarch64_sve_st1_scatter_scalar_offset:
2022+
case Intrinsic::aarch64_sve_st1_scatter_sxtw:
2023+
case Intrinsic::aarch64_sve_st1_scatter_sxtw_index:
2024+
case Intrinsic::aarch64_sve_st1_scatter_uxtw:
2025+
case Intrinsic::aarch64_sve_st1_scatter_uxtw_index:
2026+
case Intrinsic::aarch64_sve_st1dq:
2027+
case Intrinsic::aarch64_sve_st1q_scatter_index:
2028+
case Intrinsic::aarch64_sve_st1q_scatter_scalar_offset:
2029+
case Intrinsic::aarch64_sve_st1q_scatter_vector_offset:
2030+
case Intrinsic::aarch64_sve_st1wq:
2031+
case Intrinsic::aarch64_sve_stnt1:
2032+
case Intrinsic::aarch64_sve_stnt1_scatter:
2033+
case Intrinsic::aarch64_sve_stnt1_scatter_index:
2034+
case Intrinsic::aarch64_sve_stnt1_scatter_scalar_offset:
2035+
case Intrinsic::aarch64_sve_stnt1_scatter_uxtw:
2036+
return instCombineSVENoActiveUnaryErase(IC, II, 1);
2037+
case Intrinsic::aarch64_sve_st2:
2038+
case Intrinsic::aarch64_sve_st2q:
2039+
return instCombineSVENoActiveUnaryErase(IC, II, 2);
2040+
case Intrinsic::aarch64_sve_st3:
2041+
case Intrinsic::aarch64_sve_st3q:
2042+
return instCombineSVENoActiveUnaryErase(IC, II, 3);
2043+
case Intrinsic::aarch64_sve_st4:
2044+
case Intrinsic::aarch64_sve_st4q:
2045+
return instCombineSVENoActiveUnaryErase(IC, II, 4);
20102046
case Intrinsic::aarch64_sve_ld1_gather:
20112047
case Intrinsic::aarch64_sve_ld1_gather_scalar_offset:
20122048
case Intrinsic::aarch64_sve_ld1_gather_sxtw:

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes-stores.ll

Lines changed: 310 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,310 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
;RUN: opt -S -passes=instcombine < %s | FileCheck %s
3+
target triple = "aarch64-unknown-linux-gnu"
4+
5+
define void @test_st1(ptr %a, <vscale x 16 x i8> %b) {
6+
; CHECK-LABEL: define void @test_st1(
7+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 16 x i8> [[B:%.*]]) {
8+
; CHECK-NEXT: [[ENTRY:.*:]]
9+
; CHECK-NEXT: ret void
10+
;
11+
entry:
12+
call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %b, <vscale x 16 x i1> zeroinitializer, ptr %a)
13+
ret void
14+
}
15+
16+
define void @test_st1_scatter(<vscale x 2 x i16> %data_trunc, ptr %base, <vscale x 2 x i64> %b) {
17+
; CHECK-LABEL: define void @test_st1_scatter(
18+
; CHECK-SAME: <vscale x 2 x i16> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 2 x i64> [[B:%.*]]) {
19+
; CHECK-NEXT: [[ENTRY:.*:]]
20+
; CHECK-NEXT: ret void
21+
;
22+
entry:
23+
call void @llvm.aarch64.sve.st1.scatter.nxv2i16(<vscale x 2 x i16> %data_trunc,
24+
<vscale x 2 x i1> zeroinitializer,
25+
ptr %base,
26+
<vscale x 2 x i64> %b)
27+
ret void
28+
}
29+
30+
define void @test_st1_scatter_index(<vscale x 2 x i32> %data_trunc, ptr %base, <vscale x 2 x i64> %offsets) {
31+
; CHECK-LABEL: define void @test_st1_scatter_index(
32+
; CHECK-SAME: <vscale x 2 x i32> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 2 x i64> [[OFFSETS:%.*]]) {
33+
; CHECK-NEXT: [[ENTRY:.*:]]
34+
; CHECK-NEXT: call void @llvm.aarch64.sve.st1.scatter.index.nxv2i32(<vscale x 2 x i32> [[DATA_TRUNC]], <vscale x 2 x i1> zeroinitializer, ptr [[BASE]], <vscale x 2 x i64> [[OFFSETS]])
35+
; CHECK-NEXT: ret void
36+
;
37+
entry:
38+
call void @llvm.aarch64.sve.st1.scatter.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
39+
<vscale x 2 x i1> zeroinitializer,
40+
ptr %base,
41+
<vscale x 2 x i64> %offsets)
42+
ret void
43+
}
44+
45+
define void @test_st1_scatter_scalar_offset(<vscale x 4 x i8> %data_trunc, <vscale x 4 x i32> %base) {
46+
; CHECK-LABEL: define void @test_st1_scatter_scalar_offset(
47+
; CHECK-SAME: <vscale x 4 x i8> [[DATA_TRUNC:%.*]], <vscale x 4 x i32> [[BASE:%.*]]) {
48+
; CHECK-NEXT: [[ENTRY:.*:]]
49+
; CHECK-NEXT: ret void
50+
;
51+
entry:
52+
call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i8> %data_trunc,
53+
<vscale x 4 x i1> zeroinitializer,
54+
<vscale x 4 x i32> %base,
55+
i64 16)
56+
ret void
57+
}
58+
59+
define void @test_st1_scatter_sxtw(<vscale x 4 x i8> %data_trunc, ptr %base, <vscale x 4 x i32> %offsets) {
60+
; CHECK-LABEL: define void @test_st1_scatter_sxtw(
61+
; CHECK-SAME: <vscale x 4 x i8> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 4 x i32> [[OFFSETS:%.*]]) {
62+
; CHECK-NEXT: ret void
63+
;
64+
call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8(<vscale x 4 x i8> %data_trunc,
65+
<vscale x 4 x i1> zeroinitializer,
66+
ptr %base,
67+
<vscale x 4 x i32> %offsets)
68+
ret void
69+
}
70+
71+
define void @test_st1_scatter_sxtw_index(<vscale x 4 x i16> %data_trunc, ptr %base, <vscale x 4 x i32> %indices) {
72+
; CHECK-LABEL: define void @test_st1_scatter_sxtw_index(
73+
; CHECK-SAME: <vscale x 4 x i16> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 4 x i32> [[INDICES:%.*]]) {
74+
; CHECK-NEXT: ret void
75+
;
76+
call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,
77+
<vscale x 4 x i1> zeroinitializer,
78+
ptr %base,
79+
<vscale x 4 x i32> %indices)
80+
ret void
81+
}
82+
83+
define void @test_st1_scatter_uxtw(<vscale x 4 x i8> %data_trunc, ptr %base, <vscale x 4 x i32> %offsets) {
84+
; CHECK-LABEL: define void @test_st1_scatter_uxtw(
85+
; CHECK-SAME: <vscale x 4 x i8> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 4 x i32> [[OFFSETS:%.*]]) {
86+
; CHECK-NEXT: ret void
87+
;
88+
call void @llvm.aarch64.sve.st1.scatter.uxtw.nxv4i8(<vscale x 4 x i8> %data_trunc,
89+
<vscale x 4 x i1> zeroinitializer,
90+
ptr %base,
91+
<vscale x 4 x i32> %offsets)
92+
ret void
93+
}
94+
95+
define void @test_st1_scatter_uxtw_index(<vscale x 4 x i16> %data_trunc, ptr %base, <vscale x 4 x i32> %indices) {
96+
; CHECK-LABEL: define void @test_st1_scatter_uxtw_index(
97+
; CHECK-SAME: <vscale x 4 x i16> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 4 x i32> [[INDICES:%.*]]) {
98+
; CHECK-NEXT: ret void
99+
;
100+
call void @llvm.aarch64.sve.st1.scatter.uxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,
101+
<vscale x 4 x i1> zeroinitializer,
102+
ptr %base,
103+
<vscale x 4 x i32> %indices)
104+
ret void
105+
}
106+
107+
define void @test_st1dq(<vscale x 2 x i64> %zt, ptr %gep1) {
108+
; CHECK-LABEL: define void @test_st1dq(
109+
; CHECK-SAME: <vscale x 2 x i64> [[ZT:%.*]], ptr [[GEP1:%.*]]) {
110+
; CHECK-NEXT: [[ENTRY:.*:]]
111+
; CHECK-NEXT: ret void
112+
;
113+
entry:
114+
call void @llvm.aarch64.sve.st1dq.nxv2i64(<vscale x 2 x i64> %zt, <vscale x 1 x i1> zeroinitializer, ptr %gep1)
115+
ret void
116+
}
117+
118+
define void @test_st1q_scatter_index(<vscale x 8 x i16> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {
119+
; CHECK-LABEL: define void @test_st1q_scatter_index(
120+
; CHECK-SAME: <vscale x 8 x i16> [[DATA:%.*]], <vscale x 1 x i1> [[PG:%.*]], ptr [[BASE:%.*]], <vscale x 2 x i64> [[IDX:%.*]]) {
121+
; CHECK-NEXT: [[ENTRY:.*:]]
122+
; CHECK-NEXT: ret void
123+
;
124+
entry:
125+
call void @llvm.aarch64.sve.st1q.scatter.index.nxv8i16(<vscale x 8 x i16> %data, <vscale x 1 x i1> zeroinitializer, ptr %base, <vscale x 2 x i64> %idx)
126+
ret void
127+
}
128+
129+
define void @test_st1q_scatter_scalar_offset(<vscale x 2 x i64> %data, <vscale x 2 x i64> %base) {
130+
; CHECK-LABEL: define void @test_st1q_scatter_scalar_offset(
131+
; CHECK-SAME: <vscale x 2 x i64> [[DATA:%.*]], <vscale x 2 x i64> [[BASE:%.*]]) {
132+
; CHECK-NEXT: [[ENTRY:.*:]]
133+
; CHECK-NEXT: ret void
134+
;
135+
entry:
136+
call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %data, <vscale x 1 x i1> zeroinitializer, <vscale x 2 x i64> %base, i64 0)
137+
ret void
138+
}
139+
140+
define void @test_st1q_scatter_vector_offset(<vscale x 8 x i16> %data, ptr %base, <vscale x 2 x i64> %off) {
141+
; CHECK-LABEL: define void @test_st1q_scatter_vector_offset(
142+
; CHECK-SAME: <vscale x 8 x i16> [[DATA:%.*]], ptr [[BASE:%.*]], <vscale x 2 x i64> [[OFF:%.*]]) {
143+
; CHECK-NEXT: [[ENTRY:.*:]]
144+
; CHECK-NEXT: ret void
145+
;
146+
entry:
147+
call void @llvm.aarch64.sve.st1q.scatter.vector.offset.nxv8i16(<vscale x 8 x i16> %data, <vscale x 1 x i1> zeroinitializer, ptr %base, <vscale x 2 x i64> %off)
148+
ret void
149+
}
150+
151+
define void @test_st1wq(ptr %a, <vscale x 4 x i32> %b) {
152+
; CHECK-LABEL: define void @test_st1wq(
153+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
154+
; CHECK-NEXT: [[ENTRY:.*:]]
155+
; CHECK-NEXT: ret void
156+
;
157+
entry:
158+
call void @llvm.aarch64.sve.st1wq.nxv4i32(<vscale x 4 x i32> %b, <vscale x 1 x i1> zeroinitializer, ptr %a)
159+
ret void
160+
}
161+
162+
163+
define void @test_st2(ptr %a, <vscale x 8 x i32> %b) {
164+
; CHECK-LABEL: define void @test_st2(
165+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 8 x i32> [[B:%.*]]) {
166+
; CHECK-NEXT: [[ENTRY:.*:]]
167+
; CHECK-NEXT: ret void
168+
;
169+
entry:
170+
%0 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %b, i64 0)
171+
%1 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %b, i64 4)
172+
tail call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> zeroinitializer, ptr %a)
173+
ret void
174+
}
175+
176+
define void @test_st2q(ptr %a, <vscale x 8 x i32> %b) {
177+
; CHECK-LABEL: define void @test_st2q(
178+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 8 x i32> [[B:%.*]]) {
179+
; CHECK-NEXT: [[ENTRY:.*:]]
180+
; CHECK-NEXT: ret void
181+
;
182+
entry:
183+
%0 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %b, i64 0)
184+
%1 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %b, i64 4)
185+
tail call void @llvm.aarch64.sve.st2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> zeroinitializer, ptr %a)
186+
ret void
187+
}
188+
189+
define void @test_st3(ptr %a, <vscale x 12 x i32> %b) {
190+
; CHECK-LABEL: define void @test_st3(
191+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 12 x i32> [[B:%.*]]) {
192+
; CHECK-NEXT: [[ENTRY:.*:]]
193+
; CHECK-NEXT: ret void
194+
;
195+
entry:
196+
%0 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv12i32(<vscale x 12 x i32> %b, i64 0)
197+
%1 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv12i32(<vscale x 12 x i32> %b, i64 4)
198+
%2 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv12i32(<vscale x 12 x i32> %b, i64 8)
199+
tail call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> zeroinitializer, ptr %a)
200+
ret void
201+
}
202+
203+
define void @test_st3q(ptr %a, <vscale x 12 x i32> %b) {
204+
; CHECK-LABEL: define void @test_st3q(
205+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 12 x i32> [[B:%.*]]) {
206+
; CHECK-NEXT: [[ENTRY:.*:]]
207+
; CHECK-NEXT: ret void
208+
;
209+
entry:
210+
%0 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv12i32(<vscale x 12 x i32> %b, i64 0)
211+
%1 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv12i32(<vscale x 12 x i32> %b, i64 4)
212+
%2 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv12i32(<vscale x 12 x i32> %b, i64 8)
213+
tail call void @llvm.aarch64.sve.st3q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> zeroinitializer, ptr %a)
214+
ret void
215+
}
216+
217+
define void @test_st4(ptr %a, <vscale x 16 x i32> %b) {
218+
; CHECK-LABEL: define void @test_st4(
219+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 16 x i32> [[B:%.*]]) {
220+
; CHECK-NEXT: [[ENTRY:.*:]]
221+
; CHECK-NEXT: ret void
222+
;
223+
entry:
224+
%0 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 0)
225+
%1 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 4)
226+
%2 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 8)
227+
%3 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 12)
228+
tail call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> zeroinitializer, ptr %a)
229+
ret void
230+
}
231+
232+
define void @test_st4q(ptr %a, <vscale x 16 x i32> %b) {
233+
; CHECK-LABEL: define void @test_st4q(
234+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 16 x i32> [[B:%.*]]) {
235+
; CHECK-NEXT: [[ENTRY:.*:]]
236+
; CHECK-NEXT: ret void
237+
;
238+
entry:
239+
%0 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 0)
240+
%1 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 4)
241+
%2 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 8)
242+
%3 = tail call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %b, i64 12)
243+
tail call void @llvm.aarch64.sve.st4q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> zeroinitializer, ptr %a)
244+
ret void
245+
}
246+
247+
define void @test_stnt1(ptr %a, <vscale x 16 x i8> %b) {
248+
; CHECK-LABEL: define void @test_stnt1(
249+
; CHECK-SAME: ptr [[A:%.*]], <vscale x 16 x i8> [[B:%.*]]) {
250+
; CHECK-NEXT: [[ENTRY:.*:]]
251+
; CHECK-NEXT: ret void
252+
;
253+
entry:
254+
call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %b, <vscale x 16 x i1> zeroinitializer, ptr %a)
255+
ret void
256+
}
257+
258+
define void @test_stnt1_scatter(<vscale x 2 x i16> %data_trunc, ptr %base, <vscale x 2 x i64> %b) {
259+
; CHECK-LABEL: define void @test_stnt1_scatter(
260+
; CHECK-SAME: <vscale x 2 x i16> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 2 x i64> [[B:%.*]]) {
261+
; CHECK-NEXT: [[ENTRY:.*:]]
262+
; CHECK-NEXT: ret void
263+
;
264+
entry:
265+
call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16(<vscale x 2 x i16> %data_trunc,
266+
<vscale x 2 x i1> zeroinitializer,
267+
ptr %base,
268+
<vscale x 2 x i64> %b)
269+
ret void
270+
}
271+
272+
define void @test_stnt1_scatter_index(<vscale x 2 x i32> %data_trunc, ptr %base, <vscale x 2 x i64> %offsets) {
273+
; CHECK-LABEL: define void @test_stnt1_scatter_index(
274+
; CHECK-SAME: <vscale x 2 x i32> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 2 x i64> [[OFFSETS:%.*]]) {
275+
; CHECK-NEXT: [[ENTRY:.*:]]
276+
; CHECK-NEXT: ret void
277+
;
278+
entry:
279+
call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
280+
<vscale x 2 x i1> zeroinitializer,
281+
ptr %base,
282+
<vscale x 2 x i64> %offsets)
283+
ret void
284+
}
285+
286+
define void @test_stnt1_scatter_scalar_offset(<vscale x 4 x i8> %data_trunc, <vscale x 4 x i32> %base) {
287+
; CHECK-LABEL: define void @test_stnt1_scatter_scalar_offset(
288+
; CHECK-SAME: <vscale x 4 x i8> [[DATA_TRUNC:%.*]], <vscale x 4 x i32> [[BASE:%.*]]) {
289+
; CHECK-NEXT: [[ENTRY:.*:]]
290+
; CHECK-NEXT: ret void
291+
;
292+
entry:
293+
call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32(<vscale x 4 x i8> %data_trunc,
294+
<vscale x 4 x i1> zeroinitializer,
295+
<vscale x 4 x i32> %base,
296+
i64 16)
297+
ret void
298+
}
299+
300+
define void @test_stnt1_scatter_uxtw(<vscale x 4 x i8> %data_trunc, ptr %base, <vscale x 4 x i32> %offsets) {
301+
; CHECK-LABEL: define void @test_stnt1_scatter_uxtw(
302+
; CHECK-SAME: <vscale x 4 x i8> [[DATA_TRUNC:%.*]], ptr [[BASE:%.*]], <vscale x 4 x i32> [[OFFSETS:%.*]]) {
303+
; CHECK-NEXT: ret void
304+
;
305+
call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8(<vscale x 4 x i8> %data_trunc,
306+
<vscale x 4 x i1> zeroinitializer,
307+
ptr %base,
308+
<vscale x 4 x i32> %offsets)
309+
ret void
310+
}

0 commit comments

Comments
 (0)