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[RISCV][GISel] Narrow G_SEXT_INREG to XLenLLT before lowering.
If we lower, we need to legalize the wide shifts which is costly. This will improve the tests from https://reviews.llvm.org/D157415 too Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D157677
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3 files changed

+60
-249
lines changed

3 files changed

+60
-249
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
6868
.legalIf(ExtLegalFunc)
6969
.clampScalar(0, XLenLLT, XLenLLT);
7070

71-
getActionDefinitionsBuilder(G_SEXT_INREG).legalFor({XLenLLT}).lower();
71+
getActionDefinitionsBuilder(G_SEXT_INREG)
72+
.legalFor({XLenLLT})
73+
.maxScalar(0, XLenLLT)
74+
.lower();
7275

7376
// Merge/Unmerge
7477
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir

Lines changed: 28 additions & 124 deletions
Original file line numberDiff line numberDiff line change
@@ -94,37 +94,13 @@ body: |
9494
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
9595
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
9696
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
97-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
98-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32)
99-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
100-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32)
101-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
102-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32)
103-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
104-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
105-
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
106-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
107-
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
108-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
109-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
110-
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
111-
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
112-
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
113-
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
114-
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
115-
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
116-
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
117-
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
118-
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
119-
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
120-
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
121-
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
122-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
123-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
124-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
125-
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[OR1]](s32), [[OR3]]
126-
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
127-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
97+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
98+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
99+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
100+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
101+
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
102+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
103+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
128104
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
129105
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
130106
; CHECK-NEXT: PseudoRET implicit $x10
@@ -264,37 +240,13 @@ body: |
264240
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
265241
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
266242
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
267-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
268-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32)
269-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
270-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32)
271-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
272-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32)
273-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
274-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
275-
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
276-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
277-
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
278-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
279-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
280-
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
281-
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
282-
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
283-
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
284-
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
285-
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
286-
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
287-
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
288-
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
289-
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
290-
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
291-
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
292-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
293-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
294-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
295-
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[OR1]](s32), [[OR3]]
296-
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
297-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
243+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
244+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
245+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
246+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
247+
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
248+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
249+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
298250
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
299251
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
300252
; CHECK-NEXT: PseudoRET implicit $x10
@@ -434,37 +386,13 @@ body: |
434386
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
435387
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
436388
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
437-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
438-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32)
439-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
440-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32)
441-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
442-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32)
443-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
444-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
445-
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
446-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
447-
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
448-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
449-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
450-
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
451-
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
452-
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
453-
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
454-
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
455-
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
456-
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
457-
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
458-
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
459-
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
460-
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
461-
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
462-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
463-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]]
464-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
465-
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[OR1]](s32), [[OR3]]
466-
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
467-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
389+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
390+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
391+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
392+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
393+
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
394+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
395+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
468396
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
469397
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
470398
; CHECK-NEXT: PseudoRET implicit $x10
@@ -604,37 +532,13 @@ body: |
604532
; CHECK-NEXT: %xlo:_(s32) = COPY $x11
605533
; CHECK-NEXT: %yhi:_(s32) = COPY $x12
606534
; CHECK-NEXT: %ylo:_(s32) = COPY $x13
607-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
608-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32)
609-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
610-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32)
611-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
612-
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32)
613-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
614-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
615-
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
616-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
617-
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
618-
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
619-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
620-
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
621-
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
622-
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
623-
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
624-
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
625-
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
626-
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
627-
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
628-
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
629-
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
630-
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
631-
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
632-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
633-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]]
634-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
635-
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[OR1]](s32), [[OR3]]
636-
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
637-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
535+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
536+
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
537+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
538+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
539+
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
540+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
541+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
638542
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
639543
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
640544
; CHECK-NEXT: PseudoRET implicit $x10

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