Fix 50142

Fix a miss of further vectorization introduced in 50142, where we can
only achieve zext (xor (any_true), -1). Now in test case
simd-setcc-reductions.ll, it's converted to all_true.

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -3248,6 +3248,37 @@ static SDValue performSETCCCombine(SDNode *N,
   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
+  //  N           LHS     LhsL        LhsLL    LhsLR   InnerCond RHS Cond
+  // setcc (iN (bitcast (setcc vNi1 (vNiY X), <vNiY 0>, eq)),     0, eq
+  // => all_true (vNi1 X)
+  if (DCI.isBeforeLegalize() && VT.isScalarInteger() && (Cond == ISD::SETEQ) &&
+      (isNullConstant(RHS)) && LHS->getOpcode() == ISD::BITCAST) {
+    SDValue LhsL = LHS.getOperand(0);
+    EVT LhsLType = LhsL.getValueType();
+    if (LhsL.getOpcode() == ISD::SETCC) {
+      ISD::CondCode InnerCond =
+          cast<CondCodeSDNode>(LhsL->getOperand(2))->get();
+      if (InnerCond == ISD::SETEQ) {
+        SDValue LhsLL = LhsL.getOperand(0); // vNiY X
+        SDValue LhsLR = LhsL.getOperand(1); // <0>
+        unsigned NumElts = LhsLType.getVectorNumElements();
+        bool Vectorizable =
+            NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16;
+        EVT Width = MVT::getIntegerVT(128 / NumElts);
+
+        if (Vectorizable && LhsLR.getOpcode() == ISD::BUILD_VECTOR &&
+            LhsLType.isFixedLengthVector()) {
+          return DAG.getZExtOrTrunc(
+              DAG.getNode(
+                  ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+                  {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
+                   DAG.getSExtOrTrunc(
+                       LhsLL, DL, LhsLType.changeVectorElementType(Width))}),
+              DL, MVT::i1);
+        }
+      }
+    }
+  }
 
   // setcc (iN (bitcast (vNi1 X))), 0, ne
   //   ==> any_true (vNi1 X)

llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll

@@ -7,14 +7,8 @@ define i32 @all_true_16_i8(<16 x i8> %v) {
 ; CHECK-LABEL: all_true_16_i8:
 ; CHECK:         .functype all_true_16_i8 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT:    i8x16.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i8x16.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <16 x i8> %v, zeroinitializer
   %2 = bitcast <16 x i1> %1 to i16
   %3 = icmp eq i16 %2, 0
@@ -27,14 +21,8 @@ define i32 @all_true_4_i32(<4 x i32> %v) {
 ; CHECK-LABEL: all_true_4_i32:
 ; CHECK:         .functype all_true_4_i32 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT:    i32x4.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i32x4.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <4 x i32> %v, zeroinitializer
   %2 = bitcast <4 x i1> %1 to i4
   %3 = icmp eq i4 %2, 0
@@ -47,14 +35,8 @@ define i32 @all_true_8_i16(<8 x i16> %v) {
 ; CHECK-LABEL: all_true_8_i16:
 ; CHECK:         .functype all_true_8_i16 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT:    i16x8.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i16x8.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <8 x i16> %v, zeroinitializer
   %2 = bitcast <8 x i1> %1 to i8
   %3 = icmp eq i8 %2, 0
@@ -67,15 +49,9 @@ define i32 @all_true_4_i16(<4 x i16> %v) {
 ; CHECK-LABEL: all_true_4_i16:
 ; CHECK:         .functype all_true_4_i16 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT:    i16x8.eq $push1=, $0, $pop0
-; CHECK-NEXT:    i32x4.extend_low_i16x8_s $push2=, $pop1
-; CHECK-NEXT:    v128.any_true $push3=, $pop2
-; CHECK-NEXT:    i32.const $push4=, -1
-; CHECK-NEXT:    i32.xor $push5=, $pop3, $pop4
-; CHECK-NEXT:    i32.const $push6=, 1
-; CHECK-NEXT:    i32.and $push7=, $pop5, $pop6
-; CHECK-NEXT:    return $pop7
+; CHECK-NEXT:    i32x4.extend_low_i16x8_s $push0=, $0
+; CHECK-NEXT:    i32x4.all_true $push1=, $pop0
+; CHECK-NEXT:    return $pop1
   %1 = icmp eq <4 x i16> %v, zeroinitializer
   %2 = bitcast <4 x i1> %1 to i4
   %3 = icmp eq i4 %2, 0
@@ -88,14 +64,8 @@ define i32 @all_true_2_i64(<2 x i64> %v) {
 ; CHECK-LABEL: all_true_2_i64:
 ; CHECK:         .functype all_true_2_i64 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0
-; CHECK-NEXT:    i64x2.eq $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    i64x2.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <2 x i64> %v, zeroinitializer
   %2 = bitcast <2 x i1> %1 to i2
   %3 = icmp eq i2 %2, 0