[RISCV] Correct the precedence in isVRegClass (#116579)

4vtomat · web-flow · commit 9d7026500df1 · 2024-11-18T18:12:57.000+08:00
Right shift has higher precedence than bitwise and, so it should be
parentheses around &amp; operator. This case works as expected because
IsVRegClassShift is 0, other cases will fail.
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -39,7 +39,7 @@ enum {
 
 /// \returns the IsVRegClass for the register class.
 static inline bool isVRegClass(uint64_t TSFlags) {
-  return TSFlags & IsVRegClassShiftMask >> IsVRegClassShift;
+  return (TSFlags & IsVRegClassShiftMask) >> IsVRegClassShift;
 }
 
 /// \returns the LMUL for the register class.

Original file line number	Diff line number	Diff line change
`@@ -39,7 +39,7 @@ enum {`
`39`	`39`
`40`	`40`	`/// \returns the IsVRegClass for the register class.`
`41`	`41`	`static inline bool isVRegClass(uint64_t TSFlags) {`
`42`		`- return TSFlags & IsVRegClassShiftMask >> IsVRegClassShift;`
	`42`	`+ return (TSFlags & IsVRegClassShiftMask) >> IsVRegClassShift;`
`43`	`43`	`}`
`44`	`44`
`45`	`45`	`/// \returns the LMUL for the register class.`