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Generate extb[s/z], sle[u] by instruction. Remove no longer used intrinsics.
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5 files changed

+44
-65
lines changed

5 files changed

+44
-65
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -22446,24 +22446,21 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2244622446
ID = Intrinsic::riscv_cv_alu_clipu;
2244722447
break;
2244822448
case RISCV::BI__builtin_riscv_cv_alu_extbs:
22449-
ID = Intrinsic::riscv_cv_alu_extbs;
22450-
break;
22449+
return Builder.CreateSExt(Builder.CreateTrunc(Ops[0], Int8Ty), Int32Ty,
22450+
"extbs");
2245122451
case RISCV::BI__builtin_riscv_cv_alu_extbz:
22452-
ID = Intrinsic::riscv_cv_alu_extbz;
22453-
break;
22454-
case RISCV::BI__builtin_riscv_cv_alu_exths: {
22452+
return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int8Ty), Int32Ty,
22453+
"extbz");
22454+
case RISCV::BI__builtin_riscv_cv_alu_exths:
2245522455
return Builder.CreateSExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
2245622456
"exths");
22457-
}
2245822457
case RISCV::BI__builtin_riscv_cv_alu_exthz:
2245922458
return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
2246022459
"exthz");
2246122460
case RISCV::BI__builtin_riscv_cv_alu_slet:
22462-
ID = Intrinsic::riscv_cv_alu_slet;
22463-
break;
22461+
return Builder.CreateICmpSLE(Ops[0], Ops[1], "sle");
2246422462
case RISCV::BI__builtin_riscv_cv_alu_sletu:
22465-
ID = Intrinsic::riscv_cv_alu_sletu;
22466-
break;
22463+
return Builder.CreateICmpULE(Ops[0], Ops[1], "sleu");
2246722464
case RISCV::BI__builtin_riscv_cv_alu_subN:
2246822465
ID = Intrinsic::riscv_cv_alu_subN;
2246922466
break;

‎clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,9 @@
1919
// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4
2020
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4
2121
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4
22-
// CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.riscv.cv.alu.slet(i32 [[TMP2]], i32 [[TMP3]])
23-
// CHECK-NEXT: ret i32 [[TMP4]]
22+
// CHECK-NEXT: [[SLE_I:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
23+
// CHECK-NEXT: [[CONV_I:%.*]] = sext i1 [[SLE_I]] to i32
24+
// CHECK-NEXT: ret i32 [[CONV_I]]
2425
//
2526
int test_alu_slet(int32_t a, int32_t b) {
2627
return __riscv_cv_alu_slet(a, b);
@@ -40,8 +41,9 @@ int test_alu_slet(int32_t a, int32_t b) {
4041
// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4
4142
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4
4243
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4
43-
// CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.riscv.cv.alu.sletu(i32 [[TMP2]], i32 [[TMP3]])
44-
// CHECK-NEXT: ret i32 [[TMP4]]
44+
// CHECK-NEXT: [[SLEU_I:%.*]] = icmp ule i32 [[TMP2]], [[TMP3]]
45+
// CHECK-NEXT: [[CONV_I:%.*]] = sext i1 [[SLEU_I]] to i32
46+
// CHECK-NEXT: ret i32 [[CONV_I]]
4547
//
4648
int test_alu_sletu(uint32_t a, uint32_t b) {
4749
return __riscv_cv_alu_sletu(a, b);
@@ -156,8 +158,8 @@ int test_alu_exths(int16_t a) {
156158
// CHECK-NEXT: store i16 [[TMP0]], ptr [[A_ADDR_I]], align 2
157159
// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[A_ADDR_I]], align 2
158160
// CHECK-NEXT: [[CONV_I:%.*]] = zext i16 [[TMP1]] to i32
159-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.exthz(i32 [[CONV_I]])
160-
// CHECK-NEXT: ret i32 [[TMP2]]
161+
// CHECK-NEXT: [[EXTHZ_I:%.*]] = zext i16 [[TMP1]] to i32
162+
// CHECK-NEXT: ret i32 [[EXTHZ_I]]
161163
//
162164
int test_alu_exthz(uint16_t a) {
163165
return __riscv_cv_alu_exthz(a);
@@ -172,8 +174,8 @@ int test_alu_exthz(uint16_t a) {
172174
// CHECK-NEXT: store i8 [[TMP0]], ptr [[A_ADDR_I]], align 1
173175
// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[A_ADDR_I]], align 1
174176
// CHECK-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP1]] to i32
175-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.extbs(i32 [[CONV_I]])
176-
// CHECK-NEXT: ret i32 [[TMP2]]
177+
// CHECK-NEXT: [[EXTBS_I:%.*]] = sext i8 [[TMP1]] to i32
178+
// CHECK-NEXT: ret i32 [[EXTBS_I]]
177179
//
178180
int test_alu_extbs(int8_t a) {
179181
return __riscv_cv_alu_extbs(a);
@@ -188,8 +190,8 @@ int test_alu_extbs(int8_t a) {
188190
// CHECK-NEXT: store i8 [[TMP0]], ptr [[A_ADDR_I]], align 1
189191
// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[A_ADDR_I]], align 1
190192
// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP1]] to i32
191-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.extbz(i32 [[CONV_I]])
192-
// CHECK-NEXT: ret i32 [[TMP2]]
193+
// CHECK-NEXT: [[EXTBZ_I:%.*]] = zext i8 [[TMP1]] to i32
194+
// CHECK-NEXT: ret i32 [[EXTBZ_I]]
193195
//
194196
int test_alu_extbz(uint8_t a) {
195197
return __riscv_cv_alu_extbz(a);

‎clang/test/CodeGen/RISCV/riscv-xcvalu.c

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,16 @@ int test_abs(int a) {
1818

1919
// CHECK-LABEL: @test_alu_slet(
2020
// CHECK-NEXT: entry:
21+
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2122
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2223
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
2324
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
2425
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
2526
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2627
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
27-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.slet(i32 [[TMP0]], i32 [[TMP1]])
28+
// CHECK-NEXT: [[SLE:%.*]] = icmp sle i32 [[TMP0]], [[TMP1]]
29+
// CHECK-NEXT: store i1 [[SLE]], ptr [[RETVAL]], align 4
30+
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
2831
// CHECK-NEXT: ret i32 [[TMP2]]
2932
//
3033
int test_alu_slet(int32_t a, int32_t b) {
@@ -33,13 +36,16 @@ int test_alu_slet(int32_t a, int32_t b) {
3336

3437
// CHECK-LABEL: @test_alu_sletu(
3538
// CHECK-NEXT: entry:
39+
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3640
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3741
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3842
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
3943
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
4044
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4145
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
42-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.sletu(i32 [[TMP0]], i32 [[TMP1]])
46+
// CHECK-NEXT: [[SLEU:%.*]] = icmp ule i32 [[TMP0]], [[TMP1]]
47+
// CHECK-NEXT: store i1 [[SLEU]], ptr [[RETVAL]], align 4
48+
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
4349
// CHECK-NEXT: ret i32 [[TMP2]]
4450
//
4551
int test_alu_sletu(uint32_t a, uint32_t b) {
@@ -67,8 +73,8 @@ int test_alu_exths(int16_t a) {
6773
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
6874
// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32
6975
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i16
70-
// CHECK-NEXT: [[EXTHS:%.*]] = zext i16 [[TMP1]] to i32
71-
// CHECK-NEXT: ret i32 [[EXTHS]]
76+
// CHECK-NEXT: [[EXTHZ:%.*]] = zext i16 [[TMP1]] to i32
77+
// CHECK-NEXT: ret i32 [[EXTHZ]]
7278
//
7379
int test_alu_exthz(uint16_t a) {
7480
return __builtin_riscv_cv_alu_exthz(a);
@@ -80,8 +86,9 @@ int test_alu_exthz(uint16_t a) {
8086
// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1
8187
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
8288
// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32
83-
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.extbs(i32 [[CONV]])
84-
// CHECK-NEXT: ret i32 [[TMP1]]
89+
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i8
90+
// CHECK-NEXT: [[EXTBS:%.*]] = sext i8 [[TMP1]] to i32
91+
// CHECK-NEXT: ret i32 [[EXTBS]]
8592
//
8693
int test_alu_extbs(int8_t a) {
8794
return __builtin_riscv_cv_alu_extbs(a);
@@ -93,8 +100,9 @@ int test_alu_extbs(int8_t a) {
93100
// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1
94101
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
95102
// CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
96-
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.extbz(i32 [[CONV]])
97-
// CHECK-NEXT: ret i32 [[TMP1]]
103+
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i8
104+
// CHECK-NEXT: [[EXTBZ:%.*]] = zext i8 [[TMP1]] to i32
105+
// CHECK-NEXT: ret i32 [[EXTBZ]]
98106
//
99107
int test_alu_extbz(uint8_t a) {
100108
return __builtin_riscv_cv_alu_extbz(a);

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -792,11 +792,7 @@ let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
792792
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
793793
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
794794
def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;
795-
796-
def : PatCoreVAluGprGpr<"slet", "SLET">;
797-
def : PatCoreVAluGprGpr<"sletu", "SLETU">;
798-
def : PatCoreVAluGpr<"extbs", "EXTBS">;
799-
def : PatCoreVAluGpr<"extbz", "EXTBZ">;
795+
def : Pat<(and (XLenVT GPR:$rs1), 0xff), (CV_EXTBZ GPR:$rs1)>;
800796

801797
defm CLIP : PatCoreVAluGprImm<int_riscv_cv_alu_clip>;
802798
defm CLIPU : PatCoreVAluGprImm<int_riscv_cv_alu_clipu>;

‎llvm/test/CodeGen/RISCV/xcvalu.ll

Lines changed: 8 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -91,47 +91,23 @@ define i32 @exthz(i16 %a) {
9191
ret i32 %1
9292
}
9393

94-
declare i32 @llvm.riscv.cv.alu.slet(i32, i32)
95-
96-
define i32 @test.cv.alu.slet(i32 %a, i32 %b) {
97-
; CHECK-LABEL: test.cv.alu.slet:
98-
; CHECK: # %bb.0:
99-
; CHECK-NEXT: cv.slet a0, a0, a1
100-
; CHECK-NEXT: ret
101-
%1 = call i32 @llvm.riscv.cv.alu.slet(i32 %a, i32 %b)
102-
ret i32 %1
103-
}
104-
105-
declare i32 @llvm.riscv.cv.alu.sletu(i32, i32)
106-
107-
define i32 @test.cv.alu.sletu(i32 %a, i32 %b) {
108-
; CHECK-LABEL: test.cv.alu.sletu:
109-
; CHECK: # %bb.0:
110-
; CHECK-NEXT: cv.sletu a0, a0, a1
111-
; CHECK-NEXT: ret
112-
%1 = call i32 @llvm.riscv.cv.alu.sletu(i32 %a, i32 %b)
113-
ret i32 %1
114-
}
115-
116-
declare i32 @llvm.riscv.cv.alu.extbs(i32)
117-
118-
define i32 @test.cv.alu.extbs(i32 %a) {
119-
; CHECK-LABEL: test.cv.alu.extbs:
94+
define i32 @extbs(i8 %a) {
95+
; CHECK-LABEL: extbs:
12096
; CHECK: # %bb.0:
97+
; CHECK-NEXT: # kill: def $x11 killed $x10
12198
; CHECK-NEXT: cv.extbs a0, a0
12299
; CHECK-NEXT: ret
123-
%1 = call i32 @llvm.riscv.cv.alu.extbs(i32 %a)
100+
%1 = sext i8 %a to i32
124101
ret i32 %1
125102
}
126103

127-
declare i32 @llvm.riscv.cv.alu.extbz(i32)
128-
129-
define i32 @test.cv.alu.extbz(i32 %a) {
130-
; CHECK-LABEL: test.cv.alu.extbz:
104+
define i32 @extbz(i8 %a) {
105+
; CHECK-LABEL: extbz:
131106
; CHECK: # %bb.0:
107+
; CHECK-NEXT: # kill: def $x11 killed $x10
132108
; CHECK-NEXT: cv.extbz a0, a0
133109
; CHECK-NEXT: ret
134-
%1 = call i32 @llvm.riscv.cv.alu.extbz(i32 %a)
110+
%1 = zext i8 %a to i32
135111
ret i32 %1
136112
}
137113

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