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[fixup] Tweak the integration test
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// REQUIRES: arm-emulator
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// DEFINE: %{compile} = mlir-opt %s \
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// DEFINE: --arm-sve-legalize-vector-storage --convert-vector-to-scf --convert-scf-to-cf --convert-vector-to-llvm='enable-arm-sve' \
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// DEFINE: --expand-strided-metadata --lower-affine --convert-to-llvm --finalize-memref-to-llvm --reconcile-unrealized-casts \
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// DEFINE: -o %t
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// DEFINE: %{entry_point} = main
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// DEFINE: %{run} = %mcr_aarch64_cmd %t -e %{entry_point} -entry-point-result=void --march=aarch64 --mattr="+sve" \
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// DEFINE: -shared-libs=%mlir_runner_utils,%mlir_c_runner_utils,%native_mlir_arm_runner_utils
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// RUN: rm -f %t && %{compile} && %{run} | FileCheck %s
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// Test the transfer_read with vector type with a non-trailing scalable
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// dimension as transformed by the pattern LegalizeTransferRead.
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func.func @transfer_read_scalable_non_trailing(%vs : i32, %M : memref<?x8xi8>) {
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func.call @setArmVLBits(%vs) : (i32) -> ()
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// Read an LLVM-illegal vector
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%c0 = arith.constant 0 : index
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%c0_i8 = arith.constant 0 : i8
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%A = vector.transfer_read %M[%c0, %c0], %c0_i8 {in_bounds = [true, true]} : memref<?x8xi8>, vector<[4]x8xi8>
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// Print the vector, for verification.
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%B = vector.shape_cast %A : vector<[4]x8xi8> to vector<[32]xi8>
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func.call @printVec(%B) : (vector<[32]xi8>) -> ()
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return
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}
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func.func @main() {
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%c0 = arith.constant 0 : index
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// Prepare an 8x8 buffer with test data. The test performs two reads
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// of a [4]x8 vector from the buffer. One read, with vector length 128 bits,
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// reads the first half the buffer. The other read, with vector length
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// 256 bits, reads the entire buffer.
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%T = arith.constant dense<[[11, 12, 13, 14, 15, 16, 17, 18],
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[21, 22, 23, 24, 25, 26, 27, 28],
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[31, 32, 33, 34, 35, 36, 37, 38],
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[41, 42, 43, 44, 45, 46, 47, 48],
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[51, 52, 53, 54, 55, 56, 57, 58],
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[61, 62, 63, 64, 65, 66, 67, 68],
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[71, 72, 73, 74, 75, 76, 77, 78],
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[81, 82, 83, 84, 85, 86, 87, 88]]> : vector<8x8xi8>
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%M = memref.alloca() : memref<8x8xi8>
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vector.transfer_write %T, %M[%c0, %c0] : vector<8x8xi8>, memref<8x8xi8>
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%MM = memref.cast %M : memref<8x8xi8> to memref<?x8xi8>
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// CHECK-LABEL: Result(VL128):
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// CHECK:( 11, 12, 13, 14, 15, 16, 17, 18, 21, 22, 23, 24, 25, 26, 27, 28 )
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// CHECK:( 31, 32, 33, 34, 35, 36, 37, 38, 41, 42, 43, 44, 45, 46, 47, 48 )
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vector.print str "Result(VL128):\n"
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%c128 = arith.constant 128 : i32
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func.call @transfer_read_scalable_non_trailing(%c128, %MM) : (i32, memref<?x8xi8>) -> ()
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// CHECK-LABEL: Result(VL256):
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// CHECK: ( 11, 12, 13, 14, 15, 16, 17, 18, 21, 22, 23, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38, 41, 42, 43, 44, 45, 46, 47, 48 )
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// CHECK: ( 51, 52, 53, 54, 55, 56, 57, 58, 61, 62, 63, 64, 65, 66, 67, 68, 71, 72, 73, 74, 75, 76, 77, 78, 81, 82, 83, 84, 85, 86, 87, 88 )
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vector.print str "Result(VL256):\n"
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%c256 = arith.constant 256 : i32
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func.call @transfer_read_scalable_non_trailing(%c256, %MM) : (i32, memref<?x8xi8>) -> ()
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return
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}
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func.func private @printVec(%v : vector<[32]xi8>) {
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%v0 = vector.scalable.extract %v[0] : vector<[16]xi8> from vector<[32]xi8>
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%v1 = vector.scalable.extract %v[16] : vector<[16]xi8> from vector<[32]xi8>
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vector.print %v0 : vector<[16]xi8>
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vector.print %v1 : vector<[16]xi8>
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return
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}
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func.func private @setArmVLBits(%bits : i32)

mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-not-rightmost.mlir

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