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[ARM] Use MCRegister instead of unsigned. NFC
Primarily around uses of getSubReg/getSuperReg.
1 parent 7786266 commit 9d9c561

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7 files changed

+61
-56
lines changed

7 files changed

+61
-56
lines changed

‎llvm/lib/Target/ARM/A15SDOptimizer.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -142,9 +142,10 @@ bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
142142
}
143143

144144
unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
145-
unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
146-
&ARM::DPRRegClass);
147-
if (DReg != ARM::NoRegister) return ARM::ssub_1;
145+
MCRegister DReg =
146+
TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
147+
if (DReg)
148+
return ARM::ssub_1;
148149
return ARM::ssub_0;
149150
}
150151

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 29 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -825,7 +825,7 @@ unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
825825

826826
void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
827827
MachineBasicBlock::iterator I,
828-
unsigned DestReg, bool KillSrc,
828+
MCRegister DestReg, bool KillSrc,
829829
const ARMSubtarget &Subtarget) const {
830830
unsigned Opc = Subtarget.isThumb()
831831
? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
@@ -845,7 +845,7 @@ void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
845845

846846
void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
847847
MachineBasicBlock::iterator I,
848-
unsigned SrcReg, bool KillSrc,
848+
MCRegister SrcReg, bool KillSrc,
849849
const ARMSubtarget &Subtarget) const {
850850
unsigned Opc = Subtarget.isThumb()
851851
? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
@@ -1727,10 +1727,10 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
17271727
return false;
17281728

17291729
const TargetRegisterInfo *TRI = &getRegisterInfo();
1730-
unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1731-
&ARM::DPRRegClass);
1732-
unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1733-
&ARM::DPRRegClass);
1730+
MCRegister DstRegD =
1731+
TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, &ARM::DPRRegClass);
1732+
MCRegister SrcRegD =
1733+
TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, &ARM::DPRRegClass);
17341734
if (!DstRegD || !SrcRegD)
17351735
return false;
17361736

@@ -2594,7 +2594,7 @@ bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
25942594
// Now try to find enough space in the reglist to allocate NumBytes.
25952595
for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
25962596
--CurRegEnc) {
2597-
unsigned CurReg = RegClass->getRegister(CurRegEnc);
2597+
MCRegister CurReg = RegClass->getRegister(CurRegEnc);
25982598
if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7))
25992599
continue;
26002600
if (!IsPop) {
@@ -5089,13 +5089,14 @@ ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
50895089
return std::make_pair(ExeGeneric, 0);
50905090
}
50915091

5092-
static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
5093-
unsigned SReg, unsigned &Lane) {
5094-
unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
5092+
static MCRegister getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
5093+
unsigned SReg, unsigned &Lane) {
5094+
MCRegister DReg =
5095+
TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
50955096
Lane = 0;
50965097

5097-
if (DReg != ARM::NoRegister)
5098-
return DReg;
5098+
if (DReg)
5099+
return DReg;
50995100

51005101
Lane = 1;
51015102
DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
@@ -5120,12 +5121,13 @@ static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
51205121
/// (including the case where the DPR itself is defined), it should not.
51215122
///
51225123
static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
5123-
MachineInstr &MI, unsigned DReg,
5124-
unsigned Lane, unsigned &ImplicitSReg) {
5124+
MachineInstr &MI, MCRegister DReg,
5125+
unsigned Lane,
5126+
MCRegister &ImplicitSReg) {
51255127
// If the DPR is defined or used already, the other SPR lane will be chained
51265128
// correctly, so there is nothing to be done.
51275129
if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
5128-
ImplicitSReg = 0;
5130+
ImplicitSReg = MCRegister();
51295131
return true;
51305132
}
51315133

@@ -5142,13 +5144,14 @@ static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
51425144

51435145
// If the register is known not to be live, there is no need to add an
51445146
// implicit-use.
5145-
ImplicitSReg = 0;
5147+
ImplicitSReg = MCRegister();
51465148
return true;
51475149
}
51485150

51495151
void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
51505152
unsigned Domain) const {
5151-
unsigned DstReg, SrcReg, DReg;
5153+
unsigned DstReg, SrcReg;
5154+
MCRegister DReg;
51525155
unsigned Lane;
51535156
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
51545157
const TargetRegisterInfo *TRI = &getRegisterInfo();
@@ -5218,7 +5221,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
52185221

52195222
DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
52205223

5221-
unsigned ImplicitSReg;
5224+
MCRegister ImplicitSReg;
52225225
if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
52235226
break;
52245227

@@ -5237,7 +5240,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
52375240
// The narrower destination must be marked as set to keep previous chains
52385241
// in place.
52395242
MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5240-
if (ImplicitSReg != 0)
5243+
if (ImplicitSReg)
52415244
MIB.addReg(ImplicitSReg, RegState::Implicit);
52425245
break;
52435246
}
@@ -5249,11 +5252,12 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
52495252
DstReg = MI.getOperand(0).getReg();
52505253
SrcReg = MI.getOperand(1).getReg();
52515254

5252-
unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
5255+
unsigned DstLane = 0, SrcLane = 0;
5256+
MCRegister DDst, DSrc;
52535257
DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
52545258
DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
52555259

5256-
unsigned ImplicitSReg;
5260+
MCRegister ImplicitSReg;
52575261
if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
52585262
break;
52595263

@@ -5273,7 +5277,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
52735277
// more, so add them in manually.
52745278
MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
52755279
MIB.addReg(SrcReg, RegState::Implicit);
5276-
if (ImplicitSReg != 0)
5280+
if (ImplicitSReg)
52775281
MIB.addReg(ImplicitSReg, RegState::Implicit);
52785282
break;
52795283
}
@@ -5297,7 +5301,7 @@ void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
52975301
// On the first instruction, both DSrc and DDst may be undef if present.
52985302
// Specifically when the original instruction didn't have them as an
52995303
// <imp-use>.
5300-
unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
5304+
MCRegister CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
53015305
bool CurUndef = !MI.readsRegister(CurReg, TRI);
53025306
NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
53035307

@@ -5402,8 +5406,8 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
54025406
return 0;
54035407
} else if (ARM::SPRRegClass.contains(Reg)) {
54045408
// Physical register: MI must define the full D-reg.
5405-
unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
5406-
&ARM::DPRRegClass);
5409+
MCRegister DReg =
5410+
TRI->getMatchingSuperReg(Reg, ARM::ssub_0, &ARM::DPRRegClass);
54075411
if (!DReg || !MI.definesRegister(DReg, TRI))
54085412
return 0;
54095413
}

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -201,10 +201,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
201201
int &FrameIndex) const override;
202202

203203
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
204-
unsigned SrcReg, bool KillSrc,
204+
MCRegister SrcReg, bool KillSrc,
205205
const ARMSubtarget &Subtarget) const;
206206
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
207-
unsigned DestReg, bool KillSrc,
207+
MCRegister DestReg, bool KillSrc,
208208
const ARMSubtarget &Subtarget) const;
209209

210210
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -334,12 +334,12 @@ ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
334334
}
335335

336336
// Get the other register in a GPRPair.
337-
static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,
338-
const MCRegisterInfo *RI) {
337+
static MCRegister getPairedGPR(MCRegister Reg, bool Odd,
338+
const MCRegisterInfo *RI) {
339339
for (MCPhysReg Super : RI->superregs(Reg))
340340
if (ARM::GPRPairRegClass.contains(Super))
341341
return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);
342-
return 0;
342+
return MCRegister();
343343
}
344344

345345
// Resolve the RegPairEven / RegPairOdd register allocator hints.
@@ -390,7 +390,7 @@ bool ARMBaseRegisterInfo::getRegAllocationHints(
390390
if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
391391
continue;
392392
// Don't provide hints that are paired to a reserved register.
393-
MCPhysReg Paired = getPairedGPR(Reg, !Odd, this);
393+
MCRegister Paired = getPairedGPR(Reg, !Odd, this);
394394
if (!Paired || MRI.isReserved(Paired))
395395
continue;
396396
Hints.push_back(Reg);

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ namespace ARMRI {
4141

4242
} // end namespace ARMRI
4343

44-
static inline bool isCalleeSavedRegister(unsigned Reg,
44+
static inline bool isCalleeSavedRegister(MCRegister Reg,
4545
const MCPhysReg *CSRegs) {
4646
for (unsigned i = 0; CSRegs[i]; ++i)
4747
if (Reg == CSRegs[i])

‎llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -516,8 +516,8 @@ static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
516516
/// corresponding to the specified register spacing. Not all of the results
517517
/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
518518
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
519-
const TargetRegisterInfo *TRI, unsigned &D0,
520-
unsigned &D1, unsigned &D2, unsigned &D3) {
519+
const TargetRegisterInfo *TRI, MCRegister &D0,
520+
MCRegister &D1, MCRegister &D2, MCRegister &D3) {
521521
if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
522522
D0 = TRI->getSubReg(Reg, ARM::dsub_0);
523523
D1 = TRI->getSubReg(Reg, ARM::dsub_1);
@@ -585,11 +585,11 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
585585
SubRegIndex = ARM::dsub_1;
586586
}
587587
Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);
588-
unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
589-
&ARM::DPairSpcRegClass);
588+
MCRegister DstRegPair =
589+
TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, &ARM::DPairSpcRegClass);
590590
MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
591591
} else {
592-
unsigned D0, D1, D2, D3;
592+
MCRegister D0, D1, D2, D3;
593593
GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
594594
MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
595595
if (NumRegs > 1 && TableEntry->copyAllListRegs)
@@ -715,7 +715,7 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
715715
bool SrcIsKill = MI.getOperand(OpIdx).isKill();
716716
bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
717717
Register SrcReg = MI.getOperand(OpIdx++).getReg();
718-
unsigned D0, D1, D2, D3;
718+
MCRegister D0, D1, D2, D3;
719719
GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
720720
MIB.addReg(D0, getUndefRegState(SrcIsUndef));
721721
if (NumRegs > 1 && TableEntry->copyAllListRegs)
@@ -769,7 +769,7 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
769769
}
770770
assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
771771

772-
unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
772+
MCRegister D0, D1, D2, D3;
773773
unsigned DstReg = 0;
774774
bool DstIsDead = false;
775775
if (TableEntry->IsLoad) {
@@ -851,7 +851,7 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
851851

852852
bool SrcIsKill = MI.getOperand(OpIdx).isKill();
853853
Register SrcReg = MI.getOperand(OpIdx++).getReg();
854-
unsigned D0, D1, D2, D3;
854+
MCRegister D0, D1, D2, D3;
855855
GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
856856
MIB.addReg(D0);
857857

@@ -1547,7 +1547,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
15471547
} else {
15481548
// For big-endian targets we need to load the two subregisters of Reg
15491549
// manually because VLDRD would load them in wrong order
1550-
unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);
1550+
MCRegister SReg0 = TRI->getSubReg(Reg, ARM::ssub_0);
15511551
BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0)
15521552
.addReg(ARM::SP)
15531553
.addImm((Reg - ARM::D0) * 2)

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1917,8 +1917,8 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
19171917
// 16-byte aligned vst1.64 with 4 d-regs and address writeback.
19181918
// The writeback is only needed when emitting two vst1.64 instructions.
19191919
if (NumAlignedDPRCS2Regs >= 6) {
1920-
unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1921-
&ARM::QQPRRegClass);
1920+
MCRegister SupReg =
1921+
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
19221922
MBB.addLiveIn(SupReg);
19231923
BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
19241924
.addReg(ARM::R4, RegState::Kill)
@@ -1936,8 +1936,8 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
19361936

19371937
// 16-byte aligned vst1.64 with 4 d-regs, no writeback.
19381938
if (NumAlignedDPRCS2Regs >= 4) {
1939-
unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1940-
&ARM::QQPRRegClass);
1939+
MCRegister SupReg =
1940+
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
19411941
MBB.addLiveIn(SupReg);
19421942
BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
19431943
.addReg(ARM::R4)
@@ -1951,8 +1951,8 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
19511951

19521952
// 16-byte aligned vst1.64 with 2 d-regs.
19531953
if (NumAlignedDPRCS2Regs >= 2) {
1954-
unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1955-
&ARM::QPRRegClass);
1954+
MCRegister SupReg =
1955+
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass);
19561956
MBB.addLiveIn(SupReg);
19571957
BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
19581958
.addReg(ARM::R4)
@@ -2049,8 +2049,8 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
20492049

20502050
// 16-byte aligned vld1.64 with 4 d-regs and writeback.
20512051
if (NumAlignedDPRCS2Regs >= 6) {
2052-
unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
2053-
&ARM::QQPRRegClass);
2052+
MCRegister SupReg =
2053+
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
20542054
BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
20552055
.addReg(ARM::R4, RegState::Define)
20562056
.addReg(ARM::R4, RegState::Kill)
@@ -2067,8 +2067,8 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
20672067

20682068
// 16-byte aligned vld1.64 with 4 d-regs, no writeback.
20692069
if (NumAlignedDPRCS2Regs >= 4) {
2070-
unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
2071-
&ARM::QQPRRegClass);
2070+
MCRegister SupReg =
2071+
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);
20722072
BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
20732073
.addReg(ARM::R4)
20742074
.addImm(16)
@@ -2080,8 +2080,8 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
20802080

20812081
// 16-byte aligned vld1.64 with 2 d-regs.
20822082
if (NumAlignedDPRCS2Regs >= 2) {
2083-
unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
2084-
&ARM::QPRRegClass);
2083+
MCRegister SupReg =
2084+
TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass);
20852085
BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
20862086
.addReg(ARM::R4)
20872087
.addImm(16)

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