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[mlir][openacc] Cleanup acc.enter_data from old data clause operands
Since the new data operand operations have been added in D148389 and adopted on acc.enter_data in D148721, the old clause operands are no longer needed. The LegalizeDataOpForLLVMTranslation will become obsolete when all operations will be cleaned. For the time being only the appropriate part are being removed. processOperands will also receive some updates once all the operands will be coming from an acc data operand operation. Reviewed By: jeanPerier Differential Revision: https://reviews.llvm.org/D150132
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-179
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13 files changed

+134
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‎flang/lib/Lower/OpenACC.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1287,7 +1287,6 @@ genACCEnterDataOp(Fortran::lower::AbstractConverter &converter,
12871287
addOperand(operands, operandSegments, async);
12881288
addOperand(operands, operandSegments, waitDevnum);
12891289
addOperands(operands, operandSegments, waitOperands);
1290-
operandSegments.append({0, 0, 0, 0});
12911290
addOperands(operands, operandSegments, dataClauseOperands);
12921291

12931292
mlir::acc::EnterDataOp enterDataOp = createSimpleOp<mlir::acc::EnterDataOp>(

‎flang/lib/Optimizer/Transforms/OpenACC/OpenACCDataOperandConversion.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,6 @@ void OpenACCDataOperandConversion::runOnOperation() {
116116
fir::LLVMTypeConverter converter(
117117
op.getOperation()->getParentOfType<mlir::ModuleOp>(), true);
118118
patterns.add<LegalizeDataOpForLLVMTranslation<acc::DataOp>>(converter);
119-
patterns.add<LegalizeDataOpForLLVMTranslation<acc::EnterDataOp>>(converter);
120119
patterns.add<LegalizeDataOpForLLVMTranslation<acc::ExitDataOp>>(converter);
121120
patterns.add<LegalizeDataOpForLLVMTranslation<acc::ParallelOp>>(converter);
122121

@@ -148,14 +147,6 @@ void OpenACCDataOperandConversion::runOnOperation() {
148147
allDataOperandsAreConverted(op.getAttachOperands());
149148
});
150149

151-
target.addDynamicallyLegalOp<acc::EnterDataOp>(
152-
[allDataOperandsAreConverted](acc::EnterDataOp op) {
153-
return allDataOperandsAreConverted(op.getCopyinOperands()) &&
154-
allDataOperandsAreConverted(op.getCreateOperands()) &&
155-
allDataOperandsAreConverted(op.getCreateZeroOperands()) &&
156-
allDataOperandsAreConverted(op.getAttachOperands());
157-
});
158-
159150
target.addDynamicallyLegalOp<acc::ExitDataOp>(
160151
[allDataOperandsAreConverted](acc::ExitDataOp op) {
161152
return allDataOperandsAreConverted(op.getCopyoutOperands()) &&

‎flang/test/Transforms/OpenACC/convert-data-operands-to-llvmir.fir

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,21 +32,17 @@ fir.global internal @_QFEa : !fir.array<10xf32> {
3232

3333
func.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
3434
%0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
35-
acc.enter_data copyin(%0 : !fir.ref<!fir.array<10xf32>>)
3635
acc.exit_data copyout(%0 : !fir.ref<!fir.array<10xf32>>)
3736
return
3837
}
3938

4039
// CHECK-LABEL: func.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
4140
// CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
42-
// CHECK: %[[CAST0:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
43-
// CHECK: acc.enter_data copyin(%[[CAST0]] : !llvm.ptr<array<10 x f32>>)
4441
// CHECK: %[[CAST1:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
4542
// CHECK: acc.exit_data copyout(%[[CAST1]] : !llvm.ptr<array<10 x f32>>)
4643

4744
// LLVMIR-LABEL: llvm.func @_QQsub_enter_exit() attributes {fir.bindc_name = "a"} {
4845
// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
49-
// LLVMIR: acc.enter_data copyin(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
5046
// LLVMIR: acc.exit_data copyout(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
5147

5248
// -----

‎mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -765,10 +765,6 @@ def OpenACC_EnterDataOp : OpenACC_Op<"enter_data", [AttrSizedOperandSegments]> {
765765
Optional<IntOrIndex>:$waitDevnum,
766766
Variadic<IntOrIndex>:$waitOperands,
767767
UnitAttr:$wait,
768-
Variadic<AnyType>:$copyinOperands,
769-
Variadic<AnyType>:$createOperands,
770-
Variadic<AnyType>:$createZeroOperands,
771-
Variadic<AnyType>:$attachOperands,
772768
Variadic<OpenACC_PointerLikeTypeInterface>:$dataClauseOperands);
773769

774770
let extraClassDeclaration = [{
@@ -785,11 +781,6 @@ def OpenACC_EnterDataOp : OpenACC_Op<"enter_data", [AttrSizedOperandSegments]> {
785781
| `async` `(` $asyncOperand `:` type($asyncOperand) `)`
786782
| `wait_devnum` `(` $waitDevnum `:` type($waitDevnum) `)`
787783
| `wait` `(` $waitOperands `:` type($waitOperands) `)`
788-
| `copyin` `(` $copyinOperands `:` type($copyinOperands) `)`
789-
| `create` `(` $createOperands `:` type($createOperands) `)`
790-
| `create_zero` `(` $createZeroOperands `:`
791-
type($createZeroOperands) `)`
792-
| `attach` `(` $attachOperands `:` type($attachOperands) `)`
793784
| `dataOperands` `(` $dataClauseOperands `:` type($dataClauseOperands) `)`
794785
)
795786
attr-dict-with-keyword

‎mlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,6 @@ class LegalizeDataOpForLLVMTranslation : public ConvertOpToLLVMPattern<Op> {
156156
void mlir::populateOpenACCToLLVMConversionPatterns(
157157
LLVMTypeConverter &converter, RewritePatternSet &patterns) {
158158
patterns.add<LegalizeDataOpForLLVMTranslation<acc::DataOp>>(converter);
159-
patterns.add<LegalizeDataOpForLLVMTranslation<acc::EnterDataOp>>(converter);
160159
patterns.add<LegalizeDataOpForLLVMTranslation<acc::ExitDataOp>>(converter);
161160
patterns.add<LegalizeDataOpForLLVMTranslation<acc::ParallelOp>>(converter);
162161
}
@@ -209,14 +208,6 @@ void ConvertOpenACCToLLVMPass::runOnOperation() {
209208
allDataOperandsAreConverted(op.getAttachOperands());
210209
});
211210

212-
target.addDynamicallyLegalOp<acc::EnterDataOp>(
213-
[allDataOperandsAreConverted](acc::EnterDataOp op) {
214-
return allDataOperandsAreConverted(op.getCopyinOperands()) &&
215-
allDataOperandsAreConverted(op.getCreateOperands()) &&
216-
allDataOperandsAreConverted(op.getCreateZeroOperands()) &&
217-
allDataOperandsAreConverted(op.getAttachOperands());
218-
});
219-
220211
target.addDynamicallyLegalOp<acc::ExitDataOp>(
221212
[allDataOperandsAreConverted](acc::ExitDataOp op) {
222213
return allDataOperandsAreConverted(op.getCopyoutOperands()) &&

‎mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -588,12 +588,9 @@ LogicalResult acc::EnterDataOp::verify() {
588588
// 2.6.6. Data Enter Directive restriction
589589
// At least one copyin, create, or attach clause must appear on an enter data
590590
// directive.
591-
if (getCopyinOperands().empty() && getCreateOperands().empty() &&
592-
getCreateZeroOperands().empty() && getAttachOperands().empty() &&
593-
getDataClauseOperands().empty())
594-
return emitError(
595-
"at least one operand in copyin, create, "
596-
"create_zero or attach must appear on the enter data operation");
591+
if (getDataClauseOperands().empty())
592+
return emitError("at least one operand must be present in dataOperands on "
593+
"the enter data operation");
597594

598595
// The async attribute represent the async clause without value. Therefore the
599596
// attribute and operand cannot appear at the same time.
@@ -617,9 +614,7 @@ LogicalResult acc::EnterDataOp::verify() {
617614
}
618615

619616
unsigned EnterDataOp::getNumDataOperands() {
620-
return getCopyinOperands().size() + getCreateOperands().size() +
621-
getCreateZeroOperands().size() + getAttachOperands().size() +
622-
getDataClauseOperands().size();
617+
return getDataClauseOperands().size();
623618
}
624619

625620
Value EnterDataOp::getDataOperand(unsigned i) {

‎mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp

Lines changed: 22 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -162,16 +162,30 @@ processDataOperands(llvm::IRBuilderBase &builder,
162162
unsigned index = 0;
163163

164164
// Create operands are handled as `alloc` call.
165-
if (failed(processOperands(builder, moduleTranslation, op,
166-
op.getCreateOperands(), op.getNumDataOperands(),
167-
kCreateFlag, flags, names, index, mapperAllocas)))
165+
// Copyin operands are handled as `to` call.
166+
llvm::SmallVector<mlir::Value> create, copyin;
167+
for (mlir::Value dataOp : op.getDataClauseOperands()) {
168+
if (auto createOp =
169+
mlir::dyn_cast_or_null<acc::CreateOp>(dataOp.getDefiningOp())) {
170+
create.push_back(createOp.getVarPtr());
171+
} else if (auto copyinOp = mlir::dyn_cast_or_null<acc::CopyinOp>(
172+
dataOp.getDefiningOp())) {
173+
copyin.push_back(copyinOp.getVarPtr());
174+
}
175+
}
176+
177+
auto nbTotalOperands = create.size() + copyin.size();
178+
179+
// Create operands are handled as `alloc` call.
180+
if (failed(processOperands(builder, moduleTranslation, op, create,
181+
nbTotalOperands, kCreateFlag, flags, names, index,
182+
mapperAllocas)))
168183
return failure();
169184

170185
// Copyin operands are handled as `to` call.
171-
if (failed(processOperands(builder, moduleTranslation, op,
172-
op.getCopyinOperands(), op.getNumDataOperands(),
173-
kDeviceCopyinFlag, flags, names, index,
174-
mapperAllocas)))
186+
if (failed(processOperands(builder, moduleTranslation, op, copyin,
187+
nbTotalOperands, kDeviceCopyinFlag, flags, names,
188+
index, mapperAllocas)))
175189
return failure();
176190

177191
return success();
@@ -495,7 +509,7 @@ LogicalResult OpenACCDialectLLVMIRTranslationInterface::convertOperation(
495509
"unexpected OpenACC terminator with operands");
496510
return success();
497511
})
498-
.Case([&](acc::UpdateDeviceOp) {
512+
.Case<acc::CreateOp, acc::CopyinOp, acc::UpdateDeviceOp>([](auto op) {
499513
// NOP
500514
return success();
501515
})

‎mlir/test/Conversion/OpenACCToLLVM/convert-data-operands-to-llvmir.mlir

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,5 @@
11
// RUN: mlir-opt -convert-openacc-to-llvm='use-opaque-pointers=1' -split-input-file %s | FileCheck %s
22

3-
func.func @testenterdataop(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
4-
acc.enter_data copyin(%b : memref<10xf32>) create(%a : memref<10xf32>)
5-
return
6-
}
7-
8-
// CHECK: acc.enter_data copyin(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) create(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>)
9-
10-
// -----
11-
12-
func.func @testenterdataop(%a: !llvm.ptr, %b: memref<10xf32>) -> () {
13-
acc.enter_data copyin(%b : memref<10xf32>) create(%a : !llvm.ptr)
14-
return
15-
}
16-
17-
// CHECK: acc.enter_data copyin(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) create(%{{.*}} : !llvm.ptr)
18-
19-
// -----
20-
21-
func.func @testenterdataop(%a: memref<10xi64>, %b: memref<10xf32>) -> () {
22-
acc.enter_data copyin(%b : memref<10xf32>) create_zero(%a : memref<10xi64>) attributes {async}
23-
return
24-
}
25-
26-
// CHECK: acc.enter_data copyin(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) create_zero(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) attributes {async}
27-
28-
// -----
29-
30-
func.func @testenterdataop(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
31-
%ifCond = arith.constant true
32-
acc.enter_data if(%ifCond) copyin(%b : memref<10xf32>) create(%a : memref<10xf32>)
33-
return
34-
}
35-
36-
// CHECK: acc.enter_data if(%{{.*}}) copyin(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) create(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>)
37-
38-
// -----
39-
403
func.func @testexitdataop(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
414
acc.exit_data copyout(%b : memref<10xf32>) delete(%a : memref<10xf32>)
425
return

‎mlir/test/Conversion/OpenACCToSCF/convert-openacc-to-scf.mlir

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,14 @@
11
// RUN: mlir-opt %s -convert-openacc-to-scf -split-input-file | FileCheck %s
22

3-
func.func @testenterdataop(%a: memref<10xf32>, %ifCond: i1) -> () {
4-
acc.enter_data if(%ifCond) create(%a: memref<10xf32>)
3+
func.func @testenterdataop(%a: memref<f32>, %ifCond: i1) -> () {
4+
%0 = acc.create varPtr(%a : memref<f32>) -> memref<f32>
5+
acc.enter_data if(%ifCond) dataOperands(%0 : memref<f32>)
56
return
67
}
78

8-
// CHECK: func @testenterdataop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
9+
// CHECK: func @testenterdataop(%{{.*}}: memref<f32>, [[IFCOND:%.*]]: i1)
910
// CHECK: scf.if [[IFCOND]] {
10-
// CHECK-NEXT: acc.enter_data create(%{{.*}} : memref<10xf32>)
11+
// CHECK-NEXT: acc.enter_data dataOperands(%{{.*}} : memref<f32>)
1112
// CHECK-NEXT: }
1213

1314
// -----
@@ -62,26 +63,28 @@ func.func @update_false(%arg0: memref<f32>) {
6263

6364
// -----
6465

65-
func.func @enter_data_true(%d1 : memref<10xf32>) {
66+
func.func @enter_data_true(%d1 : memref<f32>) {
6667
%true = arith.constant true
67-
acc.enter_data if(%true) create(%d1 : memref<10xf32>) attributes {async}
68+
%0 = acc.create varPtr(%d1 : memref<f32>) -> memref<f32>
69+
acc.enter_data if(%true) dataOperands(%0 : memref<f32>) attributes {async}
6870
return
6971
}
7072

7173
// CHECK-LABEL: func.func @enter_data_true
7274
// CHECK-NOT: if
73-
// CHECK: acc.enter_data create
75+
// CHECK: acc.enter_data dataOperands
7476

7577
// -----
7678

77-
func.func @enter_data_false(%d1 : memref<10xf32>) {
79+
func.func @enter_data_false(%d1 : memref<f32>) {
7880
%false = arith.constant false
79-
acc.enter_data if(%false) create(%d1 : memref<10xf32>) attributes {async}
81+
%0 = acc.create varPtr(%d1 : memref<f32>) -> memref<f32>
82+
acc.enter_data if(%false) dataOperands(%0 : memref<f32>) attributes {async}
8083
return
8184
}
8285

8386
// CHECK-LABEL: func.func @enter_data_false
84-
// CHECK-NOT:acc.enter_data
87+
// CHECK-NOT: acc.enter_data
8588

8689
// -----
8790

‎mlir/test/Dialect/OpenACC/canonicalize.mlir

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,20 @@
11
// RUN: mlir-opt %s -canonicalize="test-convergence" -split-input-file | FileCheck %s
22

3-
func.func @testenterdataop(%a: memref<10xf32>) -> () {
3+
func.func @testenterdataop(%a: memref<f32>) -> () {
44
%ifCond = arith.constant true
5-
acc.enter_data if(%ifCond) create(%a: memref<10xf32>)
5+
%0 = acc.create varPtr(%a : memref<f32>) -> memref<f32>
6+
acc.enter_data if(%ifCond) dataOperands(%0 : memref<f32>)
67
return
78
}
89

9-
// CHECK: acc.enter_data create(%{{.*}} : memref<10xf32>)
10+
// CHECK: acc.enter_data dataOperands(%{{.*}} : memref<f32>)
1011

1112
// -----
1213

13-
func.func @testenterdataop(%a: memref<10xf32>) -> () {
14+
func.func @testenterdataop(%a: memref<f32>) -> () {
1415
%ifCond = arith.constant false
15-
acc.enter_data if(%ifCond) create(%a: memref<10xf32>)
16+
%0 = acc.create varPtr(%a : memref<f32>) -> memref<f32>
17+
acc.enter_data if(%ifCond) dataOperands(%0 : memref<f32>)
1618
return
1719
}
1820

@@ -67,13 +69,14 @@ func.func @testupdateop(%a: memref<f32>) -> () {
6769

6870
// -----
6971

70-
func.func @testenterdataop(%a: memref<10xf32>, %ifCond: i1) -> () {
71-
acc.enter_data if(%ifCond) create(%a: memref<10xf32>)
72+
func.func @testenterdataop(%a: memref<f32>, %ifCond: i1) -> () {
73+
%0 = acc.create varPtr(%a : memref<f32>) -> memref<f32>
74+
acc.enter_data if(%ifCond) dataOperands(%0 : memref<f32>)
7275
return
7376
}
7477

75-
// CHECK: func @testenterdataop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
76-
// CHECK: acc.enter_data if(%{{.*}}) create(%{{.*}} : memref<10xf32>)
78+
// CHECK: func @testenterdataop(%{{.*}}: memref<f32>, [[IFCOND:%.*]]: i1)
79+
// CHECK: acc.enter_data if(%{{.*}}) dataOperands(%{{.*}} : memref<f32>)
7780

7881
// -----
7982

‎mlir/test/Dialect/OpenACC/invalid.mlir

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -186,29 +186,32 @@ acc.exit_data wait_devnum(%cst: index) delete(%value : memref<10xf32>)
186186

187187
// -----
188188

189-
// expected-error@+1 {{at least one operand in copyin, create, create_zero or attach must appear on the enter data operation}}
189+
// expected-error@+1 {{at least one operand must be present in dataOperands on the enter data operation}}
190190
acc.enter_data attributes {async}
191191

192192
// -----
193193

194194
%cst = arith.constant 1 : index
195-
%value = memref.alloc() : memref<10xf32>
195+
%value = memref.alloc() : memref<f32>
196+
%0 = acc.create varPtr(%value : memref<f32>) -> memref<f32>
196197
// expected-error@+1 {{async attribute cannot appear with asyncOperand}}
197-
acc.enter_data async(%cst: index) create(%value : memref<10xf32>) attributes {async}
198+
acc.enter_data async(%cst: index) dataOperands(%0 : memref<f32>) attributes {async}
198199

199200
// -----
200201

201202
%cst = arith.constant 1 : index
202-
%value = memref.alloc() : memref<10xf32>
203+
%value = memref.alloc() : memref<f32>
204+
%0 = acc.create varPtr(%value : memref<f32>) -> memref<f32>
203205
// expected-error@+1 {{wait attribute cannot appear with waitOperands}}
204-
acc.enter_data wait(%cst: index) create(%value : memref<10xf32>) attributes {wait}
206+
acc.enter_data wait(%cst: index) dataOperands(%0 : memref<f32>) attributes {wait}
205207

206208
// -----
207209

208210
%cst = arith.constant 1 : index
209-
%value = memref.alloc() : memref<10xf32>
211+
%value = memref.alloc() : memref<f32>
212+
%0 = acc.create varPtr(%value : memref<f32>) -> memref<f32>
210213
// expected-error@+1 {{wait_devnum cannot appear without waitOperands}}
211-
acc.enter_data wait_devnum(%cst: index) create(%value : memref<10xf32>)
214+
acc.enter_data wait_devnum(%cst: index) dataOperands(%0 : memref<f32>)
212215

213216
// -----
214217

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