uniform creation of vregs; address call lowering & builtins

Author: VyacheslavLevytskyy

llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

@@ -404,6 +404,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   for (const auto &Arg : F.args()) {
     assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
     MRI->setRegClass(VRegs[i][0], GR->getRegClass(ArgTypeVRegs[i]));
+    MRI->setType(VRegs[i][0], GR->getRegType(ArgTypeVRegs[i]));
     MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
         .addDef(VRegs[i][0])
         .addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
@@ -532,10 +533,17 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
     SmallVector<Register, 8> ArgVRegs;
     for (auto Arg : Info.OrigArgs) {
       assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
-      ArgVRegs.push_back(Arg.Regs[0]);
-      SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
-      if (!GR->getSPIRVTypeForVReg(Arg.Regs[0]))
-        GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MF);
+      Register ArgReg = Arg.Regs[0];
+      ArgVRegs.push_back(ArgReg);
+      SPIRVType *SpvType = GR->getSPIRVTypeForVReg(ArgReg);
+      if (!SpvType) {
+        SpvType = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
+        GR->assignSPIRVTypeToVReg(SpvType, ArgReg, MF);
+      }
+      if (!MRI->getRegClassOrNull(ArgReg)) {
+        MRI->setRegClass(ArgReg, GR->getRegClass(SpvType));
+        MRI->setType(ArgReg, GR->getRegType(SpvType));
+      }
     }
     auto instructionSet = canUseOpenCL ? SPIRV::InstructionSet::OpenCL_std
                                        : SPIRV::InstructionSet::GLSL_std_450;

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

@@ -1460,6 +1460,12 @@ SPIRVGlobalRegistry::getRegClass(SPIRVType *SpvType) const {
   return &SPIRV::iIDRegClass;
 }
 
+inline unsigned getAS(SPIRVType *SpvType) {
+  return storageClassToAddressSpace(
+      static_cast<SPIRV::StorageClass::StorageClass>(
+          SpvType->getOperand(1).getImm()));
+}
+
 LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
   unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;
   switch (Opcode) {
@@ -1468,13 +1474,13 @@ LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
   case SPIRV::OpTypeBool:
     return LLT::scalar(getScalarOrVectorBitWidth(SpvType));
   case SPIRV::OpTypePointer:
-    return LLT::pointer(0, getPointerSize());
+    return LLT::pointer(getAS(SpvType), getPointerSize());
   case SPIRV::OpTypeVector: {
     SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
     LLT ET;
     switch (ElemType ? ElemType->getOpcode() : 0) {
     case SPIRV::OpTypePointer:
-      ET = LLT::pointer(0, getPointerSize());
+      ET = LLT::pointer(getAS(ElemType), getPointerSize());
       break;
     case SPIRV::OpTypeInt:
     case SPIRV::OpTypeFloat:
@@ -1484,7 +1490,8 @@ LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
     default:
       ET = LLT::scalar(64);
     }
-    return LLT::fixed_vector(2, ET);
+    return LLT::fixed_vector(
+        static_cast<unsigned>(SpvType->getOperand(2).getImm()), ET);
   }
   }
   return LLT::scalar(64);

llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

@@ -327,6 +327,7 @@ inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
                                ->getOpcode() == SPIRV::OpTypeFloat;
 }
 
+/*
 static std::pair<Register, unsigned>
 createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
                const SPIRVGlobalRegistry &GR) {
@@ -337,16 +338,18 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
   LLT SrcLLT = MRI.getType(SrcReg);
   bool IsFloat = getIsFloat(SpvType, GR);
   auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
+  bool IsVec = SrcLLT.isVector();
+  unsigned NumElements =
+      IsVec ? std::max(2U, GR.getScalarOrVectorComponentCount(SpvType)) : 1;
   if (SrcLLT.isPointer()) {
     unsigned PtrSz = GR.getPointerSize();
     NewT = LLT::pointer(0, PtrSz);
-    bool IsVec = SrcLLT.isVector();
     if (IsVec)
-      NewT = LLT::fixed_vector(2, NewT);
+      NewT = LLT::fixed_vector(NumElements, NewT);
     GetIdOp = IsVec ? SPIRV::GET_vpID : SPIRV::GET_pID;
-  } else if (SrcLLT.isVector()) {
-    NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
-    NewT = LLT::fixed_vector(2, NewT);
+  } else if (IsVec) {
+    NewT = LLT::fixed_vector(
+        NumElements, LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType)));
     GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
   } else {
     NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
@@ -355,6 +358,28 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
   MRI.setRegClass(IdReg, GR.getRegClass(SpvType));
   return {IdReg, GetIdOp};
 }
+*/
+static std::pair<Register, unsigned>
+createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
+               const SPIRVGlobalRegistry &GR) {
+  if (!SpvType)
+    SpvType = GR.getSPIRVTypeForVReg(SrcReg);
+  const TargetRegisterClass *RC = GR.getRegClass(SpvType);
+  Register Reg = MRI.createGenericVirtualRegister(GR.getRegType(SpvType));
+  MRI.setRegClass(Reg, RC);
+  unsigned GetIdOp = SPIRV::GET_ID;
+  if (RC == &SPIRV::fIDRegClass)
+    GetIdOp = SPIRV::GET_fID;
+  else if (RC == &SPIRV::pIDRegClass)
+    GetIdOp = SPIRV::GET_pID;
+  else if (RC == &SPIRV::vfIDRegClass)
+    GetIdOp = SPIRV::GET_vfID;
+  else if (RC == &SPIRV::vpIDRegClass)
+    GetIdOp = SPIRV::GET_vpID;
+  else if (RC == &SPIRV::vIDRegClass)
+    GetIdOp = SPIRV::GET_vID;
+  return {Reg, GetIdOp};
+}
 
 // Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
 // a dst of the definition, assign SPIRVType to both registers. If SpvType is