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[AMDGPU][Clang] Add builtins for gfx12 ray tracing intrinsics (#135224)
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‎clang/include/clang/Basic/BuiltinsAMDGPU.def

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Original file line numberDiff line numberDiff line change
@@ -506,6 +506,18 @@ TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4bf16, "V4yV4y*1", "nc", "g
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TARGET_BUILTIN(__builtin_amdgcn_ds_bpermute_fi_b32, "iii", "nc", "gfx12-insts")
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// For the following two builtins, the second and third return values of the
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// intrinsics are returned through the last two pointer-type function arguments.
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TARGET_BUILTIN(__builtin_amdgcn_image_bvh8_intersect_ray, "V10UiWUifUcV3fV3fUiV4UiV3f*V3f*", "nc", "gfx12-insts")
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TARGET_BUILTIN(__builtin_amdgcn_image_bvh_dual_intersect_ray, "V10UiWUifUcV3fV3fV2UiV4UiV3f*V3f*", "nc", "gfx12-insts")
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TARGET_BUILTIN(__builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn, "V2UiUiUiV4UiIi", "n", "gfx11-insts")
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TARGET_BUILTIN(__builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn, "V2UiUiUiV8UiIi", "n", "gfx12-insts")
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// The intrinsic returns {i64, i32}, the builtin returns <2 x i64>.
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// The second return value of the intrinsic is zext'ed.
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TARGET_BUILTIN(__builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn, "V2WUiUiUiV8UiIi", "n", "gfx12-insts")
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//===----------------------------------------------------------------------===//
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// WMMA builtins.
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// Postfix w32 indicates the builtin requires wavefront size of 32.

‎clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp

Lines changed: 64 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -616,19 +616,81 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
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return Builder.CreateCall(F, {NodePtr, RayExtent, RayOrigin, RayDir,
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RayInverseDir, TextureDescr});
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}
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case AMDGPU::BI__builtin_amdgcn_image_bvh8_intersect_ray:
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case AMDGPU::BI__builtin_amdgcn_image_bvh_dual_intersect_ray: {
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Intrinsic::ID IID;
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switch (BuiltinID) {
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case AMDGPU::BI__builtin_amdgcn_image_bvh8_intersect_ray:
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IID = Intrinsic::amdgcn_image_bvh8_intersect_ray;
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break;
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case AMDGPU::BI__builtin_amdgcn_image_bvh_dual_intersect_ray:
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IID = Intrinsic::amdgcn_image_bvh_dual_intersect_ray;
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break;
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}
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llvm::Value *NodePtr = EmitScalarExpr(E->getArg(0));
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llvm::Value *RayExtent = EmitScalarExpr(E->getArg(1));
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llvm::Value *InstanceMask = EmitScalarExpr(E->getArg(2));
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llvm::Value *RayOrigin = EmitScalarExpr(E->getArg(3));
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llvm::Value *RayDir = EmitScalarExpr(E->getArg(4));
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llvm::Value *Offset = EmitScalarExpr(E->getArg(5));
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llvm::Value *TextureDescr = EmitScalarExpr(E->getArg(6));
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Address RetRayOriginPtr = EmitPointerWithAlignment(E->getArg(7));
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Address RetRayDirPtr = EmitPointerWithAlignment(E->getArg(8));
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llvm::Function *IntrinsicFunc = CGM.getIntrinsic(IID);
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llvm::CallInst *CI = Builder.CreateCall(
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IntrinsicFunc, {NodePtr, RayExtent, InstanceMask, RayOrigin, RayDir,
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Offset, TextureDescr});
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llvm::Value *RetVData = Builder.CreateExtractValue(CI, 0);
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llvm::Value *RetRayOrigin = Builder.CreateExtractValue(CI, 1);
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llvm::Value *RetRayDir = Builder.CreateExtractValue(CI, 2);
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Builder.CreateStore(RetRayOrigin, RetRayOriginPtr);
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Builder.CreateStore(RetRayDir, RetRayDirPtr);
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return RetVData;
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}
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_rtn:
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn:
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn:
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn: {
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Intrinsic::ID IID;
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switch (BuiltinID) {
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_rtn:
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IID = Intrinsic::amdgcn_ds_bvh_stack_rtn;
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break;
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn:
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IID = Intrinsic::amdgcn_ds_bvh_stack_push4_pop1_rtn;
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break;
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn:
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IID = Intrinsic::amdgcn_ds_bvh_stack_push8_pop1_rtn;
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break;
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case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn:
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IID = Intrinsic::amdgcn_ds_bvh_stack_push8_pop2_rtn;
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break;
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}
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620-
case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_rtn: {
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SmallVector<Value *, 4> Args;
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for (int i = 0, e = E->getNumArgs(); i != e; ++i)
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Args.push_back(EmitScalarExpr(E->getArg(i)));
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Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_ds_bvh_stack_rtn);
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Function *F = CGM.getIntrinsic(IID);
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Value *Call = Builder.CreateCall(F, Args);
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Value *Rtn = Builder.CreateExtractValue(Call, 0);
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Value *A = Builder.CreateExtractValue(Call, 1);
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llvm::Type *RetTy = ConvertType(E->getType());
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Value *I0 = Builder.CreateInsertElement(PoisonValue::get(RetTy), Rtn,
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(uint64_t)0);
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// ds_bvh_stack_push8_pop2_rtn returns {i64, i32} but the builtin returns
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// <2 x i64>, zext the second value.
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if (A->getType()->getPrimitiveSizeInBits() <
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RetTy->getScalarType()->getPrimitiveSizeInBits())
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A = Builder.CreateZExt(A, RetTy->getScalarType());
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return Builder.CreateInsertElement(I0, A, 1);
633695
}
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case AMDGPU::BI__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4:

‎clang/test/CodeGenOpenCL/builtins-amdgcn-raytracing.cl

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,10 @@
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// RUN: -emit-llvm -cl-std=CL2.0 -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1030 -S \
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// RUN: -cl-std=CL2.0 -o - %s | FileCheck -check-prefix=ISA %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -emit-llvm \
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// RUN: -cl-std=CL2.0 -o - %s | FileCheck -check-prefix=GFX12 %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -S \
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// RUN: -cl-std=CL2.0 -o - %s | FileCheck -check-prefix=GFX12ISA %s
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711
// Test llvm.amdgcn.image.bvh.intersect.ray intrinsic.
812

@@ -12,12 +16,18 @@
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// Postfix l indicates the 1st argument is i64 and postfix h indicates
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// the 4/5-th arguments are half4.
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19+
typedef unsigned char uchar;
1520
typedef unsigned int uint;
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typedef unsigned long ulong;
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typedef float float3 __attribute__((ext_vector_type(3)));
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typedef float float4 __attribute__((ext_vector_type(4)));
1824
typedef double double4 __attribute__((ext_vector_type(4)));
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typedef half half4 __attribute__((ext_vector_type(4)));
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typedef uint uint2 __attribute__((ext_vector_type(2)));
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typedef uint uint4 __attribute__((ext_vector_type(4)));
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typedef uint uint8 __attribute__((ext_vector_type(8)));
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typedef uint uint10 __attribute__((ext_vector_type(10)));
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typedef ulong ulong2 __attribute__((ext_vector_type(2)));
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// CHECK: call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v3f32
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// ISA: image_bvh_intersect_ray
@@ -59,3 +69,71 @@ void test_image_bvh_intersect_ray_lh(global uint4* out, ulong node_ptr,
5969
ray_origin, ray_dir, ray_inv_dir, texture_descr);
6070
}
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#if __has_builtin(__builtin_amdgcn_image_bvh8_intersect_ray)
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// GFX12: call { <10 x i32>, <3 x float>, <3 x float> } @llvm.amdgcn.image.bvh8.intersect.ray(
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// GFX12: i64 %node_ptr, float %ray_extent, i8 %instance_mask, <3 x float> %ray_origin,
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// GFX12: <3 x float> %ray_dir, i32 %offset, <4 x i32> %texture_descr)
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// GFX12ISA: image_bvh8_intersect_ray
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void test_image_bvh8_intersect_ray(global uint10* ret_vdata, float3* ret_ray_origin,
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float3* ret_ray_dir, ulong node_ptr, float ray_extent, uchar instance_mask,
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float3 ray_origin, float3 ray_dir, uint offset, uint4 texture_descr)
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{
81+
*ret_vdata = __builtin_amdgcn_image_bvh8_intersect_ray(node_ptr, ray_extent,
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instance_mask, ray_origin, ray_dir, offset, texture_descr,
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ret_ray_origin, ret_ray_dir);
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}
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#endif
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#if __has_builtin(__builtin_amdgcn_image_bvh_dual_intersect_ray)
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// GFX12: call { <10 x i32>, <3 x float>, <3 x float> } @llvm.amdgcn.image.bvh.dual.intersect.ray(
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// GFX12: i64 %node_ptr, float %ray_extent, i8 %instance_mask, <3 x float> %ray_origin,
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// GFX12: <3 x float> %ray_dir, <2 x i32> %offset, <4 x i32> %texture_descr)
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// GFX12ISA: image_bvh_dual_intersect_ray
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void test_builtin_amdgcn_image_bvh_dual_intersect_ray(global uint10* ret_vdata, float3* ret_ray_origin,
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float3* ret_ray_dir, ulong node_ptr, float ray_extent, uchar instance_mask,
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float3 ray_origin, float3 ray_dir, uint2 offset, uint4 texture_descr)
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{
96+
*ret_vdata = __builtin_amdgcn_image_bvh_dual_intersect_ray(node_ptr, ray_extent,
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instance_mask, ray_origin, ray_dir, offset, texture_descr,
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ret_ray_origin, ret_ray_dir);
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}
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#endif
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#if __has_builtin(__builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn)
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// GFX12: call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.push4.pop1.rtn(
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// GFX12: i32 %addr, i32 %data0, <4 x i32> %data1, i32 0)
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// GFX12ISA: ds_bvh_stack_push4_pop1_rtn
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void test_builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn(uint* ret_vdst, uint* ret_addr,
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uint addr, uint data0, uint4 data1)
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{
109+
uint2 ret = __builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn(addr, data0, data1, /*constant offset=*/0);
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*ret_vdst = ret.x;
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*ret_addr = ret.y;
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}
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#endif
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#if __has_builtin(__builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn)
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// GFX12: call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.push8.pop1.rtn(
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// GFX12: i32 %addr, i32 %data0, <8 x i32> %data1, i32 0)
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// GFX12ISA: ds_bvh_stack_push8_pop1_rtn
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void test_builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn(uint* ret_vdst, uint* ret_addr,
120+
uint addr, uint data0, uint8 data1)
121+
{
122+
uint2 ret = __builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn(addr, data0, data1, /*constant offset=*/0);
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*ret_vdst = ret.x;
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*ret_addr = ret.y;
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}
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#endif
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#if __has_builtin(__builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn)
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// GFX12: call { i64, i32 } @llvm.amdgcn.ds.bvh.stack.push8.pop2.rtn(
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// GFX12: i32 %addr, i32 %data0, <8 x i32> %data1, i32 0)
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// GFX12ISA: ds_bvh_stack_push8_pop2_rtn
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void test_builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn(ulong* ret_vdst, uint* ret_addr,
133+
uint addr, uint data0, uint8 data1)
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{
135+
ulong2 ret = __builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn(addr, data0, data1, /*constant offset=*/0);
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*ret_vdst = ret.x;
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*ret_addr = ret.y;
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}
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#endif

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