fixup! [RISCV] Add sched model for XiangShan-NanHu

dtcxzyw · dtcxzyw · commit 9eb16bf9e1d8 · 2023-11-17T15:44:54.000+08:00
Add unsupported features.
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
@@ -24,7 +24,8 @@ def XiangShanNanHuModel : SchedMachineModel {
   let MispredictPenalty = 11; // Based on estimate of pipeline depth.
   let CompleteModel = 0;
   let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
-  let UnsupportedFeatures = [];
+  let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr, HasVInstructions,
+                             HasVInstructionsI64];
 }
 
 let SchedModel = XiangShanNanHuModel in {

Original file line number	Diff line number	Diff line change
`@@ -24,7 +24,8 @@ def XiangShanNanHuModel : SchedMachineModel {`
`24`	`24`	`let MispredictPenalty = 11; // Based on estimate of pipeline depth.`
`25`	`25`	`let CompleteModel = 0;`
`26`	`26`	`let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.`
`27`		`- let UnsupportedFeatures = [];`
	`27`	`+ let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr, HasVInstructions,`
	`28`	`+ HasVInstructionsI64];`
`28`	`29`	`}`
`29`	`30`
`30`	`31`	`let SchedModel = XiangShanNanHuModel in {`