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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -S -passes=loop-unroll -unroll-runtime < %s | FileCheck %s |
| 3 | + |
| 4 | +target triple = "x86_64-unknown-linux-gnu" |
| 5 | + |
| 6 | +define void @selsort(ptr %array) #0 { |
| 7 | +; CHECK-LABEL: define void @selsort( |
| 8 | +; CHECK-SAME: ptr [[ARRAY:%.*]]) #[[ATTR0:[0-9]+]] { |
| 9 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 10 | +; CHECK-NEXT: [[SIZE:%.*]] = getelementptr inbounds nuw i8, ptr [[ARRAY]], i64 8 |
| 11 | +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[SIZE]], align 8 |
| 12 | +; CHECK-NEXT: [[CMP21_NOT:%.*]] = icmp eq i64 [[TMP0]], 0 |
| 13 | +; CHECK-NEXT: br i1 [[CMP21_NOT]], label %[[FOR_END18:.*]], label %[[FOR_BODY_LR_PH:.*]] |
| 14 | +; CHECK: [[FOR_BODY_LR_PH]]: |
| 15 | +; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAY]], align 8 |
| 16 | +; CHECK-NEXT: br label %[[FOR_BODY:.*]] |
| 17 | +; CHECK: [[FOR_BODY]]: |
| 18 | +; CHECK-NEXT: [[BASE_022:%.*]] = phi i64 [ 0, %[[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], %[[FOR_END:.*]] ] |
| 19 | +; CHECK-NEXT: [[ADD]] = add nuw i64 [[BASE_022]], 1 |
| 20 | +; CHECK-NEXT: [[CMP318:%.*]] = icmp ult i64 [[ADD]], [[TMP0]] |
| 21 | +; CHECK-NEXT: br i1 [[CMP318]], label %[[FOR_BODY4_PREHEADER:.*]], label %[[FOR_END]] |
| 22 | +; CHECK: [[FOR_BODY4_PREHEADER]]: |
| 23 | +; CHECK-NEXT: br label %[[FOR_BODY4:.*]] |
| 24 | +; CHECK: [[FOR_BODY4]]: |
| 25 | +; CHECK-NEXT: [[MIN_020:%.*]] = phi i64 [ [[SPEC_SELECT:%.*]], %[[FOR_BODY4]] ], [ [[BASE_022]], %[[FOR_BODY4_PREHEADER]] ] |
| 26 | +; CHECK-NEXT: [[C_019:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY4]] ], [ [[ADD]], %[[FOR_BODY4_PREHEADER]] ] |
| 27 | +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[C_019]] |
| 28 | +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 |
| 29 | +; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[MIN_020]] |
| 30 | +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4 |
| 31 | +; CHECK-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP2]], [[TMP3]] |
| 32 | +; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[CMP7]], i64 [[C_019]], i64 [[MIN_020]] |
| 33 | +; CHECK-NEXT: [[INC]] = add nuw i64 [[C_019]], 1 |
| 34 | +; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i64 [[INC]], [[TMP0]] |
| 35 | +; CHECK-NEXT: br i1 [[CMP3]], label %[[FOR_BODY4]], label %[[FOR_END_LOOPEXIT:.*]] |
| 36 | +; CHECK: [[FOR_END_LOOPEXIT]]: |
| 37 | +; CHECK-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY4]] ] |
| 38 | +; CHECK-NEXT: br label %[[FOR_END]] |
| 39 | +; CHECK: [[FOR_END]]: |
| 40 | +; CHECK-NEXT: [[MIN_0_LCSSA:%.*]] = phi i64 [ [[BASE_022]], %[[FOR_BODY]] ], [ [[SPEC_SELECT_LCSSA]], %[[FOR_END_LOOPEXIT]] ] |
| 41 | +; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[MIN_0_LCSSA]] |
| 42 | +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX9]], align 4 |
| 43 | +; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[BASE_022]] |
| 44 | +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 |
| 45 | +; CHECK-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX9]], align 4 |
| 46 | +; CHECK-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX11]], align 4 |
| 47 | +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[ADD]], [[TMP0]] |
| 48 | +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_END18_LOOPEXIT:.*]], label %[[FOR_BODY]] |
| 49 | +; CHECK: [[FOR_END18_LOOPEXIT]]: |
| 50 | +; CHECK-NEXT: br label %[[FOR_END18]] |
| 51 | +; CHECK: [[FOR_END18]]: |
| 52 | +; CHECK-NEXT: ret void |
| 53 | +; |
| 54 | +entry: |
| 55 | + %size = getelementptr inbounds nuw i8, ptr %array, i64 8 |
| 56 | + %0 = load i64, ptr %size, align 8 |
| 57 | + %cmp21.not = icmp eq i64 %0, 0 |
| 58 | + br i1 %cmp21.not, label %for.end18, label %for.body.lr.ph |
| 59 | + |
| 60 | +for.body.lr.ph: ; preds = %entry |
| 61 | + %1 = load ptr, ptr %array, align 8 |
| 62 | + br label %for.body |
| 63 | + |
| 64 | +for.body: ; preds = %for.body.lr.ph, %for.end |
| 65 | + %base.022 = phi i64 [ 0, %for.body.lr.ph ], [ %add, %for.end ] |
| 66 | + %add = add nuw i64 %base.022, 1 |
| 67 | + %cmp318 = icmp ult i64 %add, %0 |
| 68 | + br i1 %cmp318, label %for.body4, label %for.end |
| 69 | + |
| 70 | +for.body4: ; preds = %for.body, %for.body4 |
| 71 | + %min.020 = phi i64 [ %spec.select, %for.body4 ], [ %base.022, %for.body ] |
| 72 | + %c.019 = phi i64 [ %inc, %for.body4 ], [ %add, %for.body ] |
| 73 | + %arrayidx = getelementptr inbounds i32, ptr %1, i64 %c.019 |
| 74 | + %2 = load i32, ptr %arrayidx, align 4 |
| 75 | + %arrayidx6 = getelementptr inbounds i32, ptr %1, i64 %min.020 |
| 76 | + %3 = load i32, ptr %arrayidx6, align 4 |
| 77 | + %cmp7 = icmp ult i32 %2, %3 |
| 78 | + %spec.select = select i1 %cmp7, i64 %c.019, i64 %min.020 |
| 79 | + %inc = add nuw i64 %c.019, 1 |
| 80 | + %cmp3 = icmp ult i64 %inc, %0 |
| 81 | + br i1 %cmp3, label %for.body4, label %for.end |
| 82 | + |
| 83 | +for.end: ; preds = %for.body4, %for.body |
| 84 | + %min.0.lcssa = phi i64 [ %base.022, %for.body ], [ %spec.select, %for.body4 ] |
| 85 | + %arrayidx9 = getelementptr inbounds i32, ptr %1, i64 %min.0.lcssa |
| 86 | + %4 = load i32, ptr %arrayidx9, align 4 |
| 87 | + %arrayidx11 = getelementptr inbounds i32, ptr %1, i64 %base.022 |
| 88 | + %5 = load i32, ptr %arrayidx11, align 4 |
| 89 | + store i32 %5, ptr %arrayidx9, align 4 |
| 90 | + store i32 %4, ptr %arrayidx11, align 4 |
| 91 | + %exitcond.not = icmp eq i64 %add, %0 |
| 92 | + br i1 %exitcond.not, label %for.end18, label %for.body |
| 93 | + |
| 94 | +for.end18: ; preds = %for.end, %entry |
| 95 | + ret void |
| 96 | +} |
| 97 | + |
| 98 | +attributes #0 = { "tune-cpu"="generic" } |
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