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[LV] Reorganize index select tests (NFC).
This reorganizes the test coverage for selecting the min/max index. It adds coverage for umin,umax,smin,smax variants, including test-coverage for interleave codegen and cost-model driven tests.
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8 files changed

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‎llvm/test/Transforms/LoopVectorize/AArch64/select-index.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macosx -S %s | FileCheck %s
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define i64 @test_vectorize_select_umin_first_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_umin_first_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
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%gep = getelementptr i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep
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%cmp = icmp ugt i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}
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define i64 @test_vectorize_select_umin_last_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_umin_last_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umin.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
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%gep = getelementptr i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep
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%cmp = icmp uge i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.umin.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}
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define i64 @test_vectorize_select_smin_first_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_smin_first_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.smin.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
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%gep = getelementptr i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep
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%cmp = icmp sgt i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.smin.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}
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define i64 @test_vectorize_select_smin_last_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_smin_last_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp sge i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.smin.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
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%gep = getelementptr i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep
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%cmp = icmp sge i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.smin.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}
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define i64 @test_vectorize_select_umax_first_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_umax_first_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umax.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
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%gep = getelementptr i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep
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%cmp = icmp ult i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.umax.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}
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define i64 @test_vectorize_select_umax_last_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_umax_last_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.umax.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
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%gep = getelementptr i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep
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%cmp = icmp ule i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.umax.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}
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define i64 @test_vectorize_select_smax_first_idx(ptr %src, i64 %n) {
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; CHECK-LABEL: define i64 @test_vectorize_select_smax_first_idx(
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; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.smax.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
275+
; CHECK-NEXT: ret i64 [[RES]]
276+
;
277+
entry:
278+
br label %loop
279+
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loop:
281+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
282+
%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
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%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
284+
%gep = getelementptr i64, ptr %src, i64 %iv
285+
%l = load i64, ptr %gep
286+
%cmp = icmp slt i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.smax.i64(i64 %min.val, i64 %l)
288+
%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
289+
%iv.next = add nuw nsw i64 %iv, 1
290+
%exitcond.not = icmp eq i64 %iv.next, %n
291+
br i1 %exitcond.not, label %exit, label %loop
292+
293+
exit:
294+
%res = phi i64 [ %min.idx.next, %loop ]
295+
ret i64 %res
296+
}
297+
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define i64 @test_vectorize_select_smax_last_idx(ptr %src, i64 %n) {
299+
; CHECK-LABEL: define i64 @test_vectorize_select_smax_last_idx(
300+
; CHECK-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
301+
; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
303+
; CHECK: [[LOOP]]:
304+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
305+
; CHECK-NEXT: [[MIN_IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_IDX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[MIN_VAL_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[MIN_VAL]], [[L]]
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; CHECK-NEXT: [[MIN_VAL_NEXT]] = tail call i64 @llvm.smax.i64(i64 [[MIN_VAL]], i64 [[L]])
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; CHECK-NEXT: [[MIN_IDX_NEXT]] = select i1 [[CMP]], i64 [[IV]], i64 [[MIN_IDX]]
312+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
314+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[MIN_IDX_NEXT]], %[[LOOP]] ]
317+
; CHECK-NEXT: ret i64 [[RES]]
318+
;
319+
entry:
320+
br label %loop
321+
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loop:
323+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
324+
%min.idx = phi i64 [ 0, %entry ], [ %min.idx.next, %loop ]
325+
%min.val = phi i64 [ 0, %entry ], [ %min.val.next, %loop ]
326+
%gep = getelementptr i64, ptr %src, i64 %iv
327+
%l = load i64, ptr %gep
328+
%cmp = icmp sle i64 %min.val, %l
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%min.val.next = tail call i64 @llvm.smax.i64(i64 %min.val, i64 %l)
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%min.idx.next = select i1 %cmp, i64 %iv, i64 %min.idx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i64 [ %min.idx.next, %loop ]
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ret i64 %res
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}

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