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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 |
| 2 | +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s |
| 3 | + |
| 4 | +%struct.UFP = type { i32, i32, i32, [4 x i32] } |
| 5 | + |
| 6 | +define void @test(ptr %u) { |
| 7 | +; CHECK-LABEL: define void @test( |
| 8 | +; CHECK-SAME: ptr [[U:%.*]]) { |
| 9 | +; CHECK-NEXT: entry: |
| 10 | +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr null, align 4 |
| 11 | +; CHECK-NEXT: [[IDX:%.*]] = getelementptr [[STRUCT_UFP:%.*]], ptr [[U]], i64 0, i32 3, i64 3 |
| 12 | +; CHECK-NEXT: [[IDX1:%.*]] = getelementptr [[STRUCT_UFP]], ptr [[U]], i64 0, i32 3, i64 2 |
| 13 | +; CHECK-NEXT: [[IDX2:%.*]] = load i32, ptr [[IDX]], align 4 |
| 14 | +; CHECK-NEXT: [[IDX3:%.*]] = load i32, ptr [[IDX1]], align 4 |
| 15 | +; CHECK-NEXT: br label [[WHILE:%.*]] |
| 16 | +; CHECK: bb: |
| 17 | +; CHECK-NEXT: store i32 [[OR_I_I:%.*]], ptr [[IDX]], align 4 |
| 18 | +; CHECK-NEXT: store i32 [[OR19_I_I:%.*]], ptr [[IDX1]], align 4 |
| 19 | +; CHECK-NEXT: ret void |
| 20 | +; CHECK: while: |
| 21 | +; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[OR26_I_I:%.*]], [[WHILE]] ] |
| 22 | +; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[IDX3]], [[ENTRY]] ], [ [[OR19_I_I]], [[WHILE]] ] |
| 23 | +; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[IDX2]], [[ENTRY]] ], [ 0, [[WHILE]] ] |
| 24 | +; CHECK-NEXT: [[OR_I_I]] = tail call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 0, i32 0) |
| 25 | +; CHECK-NEXT: [[OR19_I_I]] = tail call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 0) |
| 26 | +; CHECK-NEXT: [[OR26_I_I]] = tail call i32 @llvm.fshl.i32(i32 0, i32 [[TMP1]], i32 0) |
| 27 | +; CHECK-NEXT: br i1 false, label [[BB:%.*]], label [[WHILE]] |
| 28 | +; |
| 29 | +entry: |
| 30 | + %0 = load i32, ptr null, align 4 |
| 31 | + %idx = getelementptr %struct.UFP, ptr %u, i64 0, i32 3, i64 3 |
| 32 | + %idx1 = getelementptr %struct.UFP, ptr %u, i64 0, i32 3, i64 2 |
| 33 | + %idx2 = load i32, ptr %idx, align 4 |
| 34 | + %idx3 = load i32, ptr %idx1, align 4 |
| 35 | + br label %while |
| 36 | + |
| 37 | +bb: |
| 38 | + store i32 %or.i.i, ptr %idx, align 4 |
| 39 | + store i32 %or19.i.i, ptr %idx1, align 4 |
| 40 | + ret void |
| 41 | + |
| 42 | +while: |
| 43 | + %1 = phi i32 [ %0, %entry ], [ %or26.i.i, %while ] |
| 44 | + %2 = phi i32 [ %idx3, %entry ], [ %or19.i.i, %while ] |
| 45 | + %3 = phi i32 [ %idx2, %entry ], [ 0, %while ] |
| 46 | + %or.i.i = tail call i32 @llvm.fshl.i32(i32 %2, i32 0, i32 0) |
| 47 | + %or19.i.i = tail call i32 @llvm.fshl.i32(i32 %1, i32 %2, i32 0) |
| 48 | + %or26.i.i = tail call i32 @llvm.fshl.i32(i32 0, i32 %1, i32 0) |
| 49 | + br i1 false, label %bb, label %while |
| 50 | +} |
| 51 | + |
| 52 | +declare i32 @llvm.fshl.i32(i32, i32, i32) |
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