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[SelectionDAG] Allow FREEZE to be hoisted before integer SETCC.
Add integer ISD::SETCC to canCreateUndefOrPoison. Add ISD::CONDCODE to isGuaranteedNotToBeUndefOrPoison. Recovers some regression from #84232.
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7 files changed

+99
-114
lines changed

7 files changed

+99
-114
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4998,6 +4998,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
49984998
return true;
49994999

50005000
switch (Opcode) {
5001+
case ISD::CONDCODE:
50015002
case ISD::VALUETYPE:
50025003
case ISD::FrameIndex:
50035004
case ISD::TargetFrameIndex:
@@ -5090,6 +5091,11 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
50905091
case ISD::BUILD_PAIR:
50915092
return false;
50925093

5094+
case ISD::SETCC:
5095+
// Integer setcc cannot create undef or poison.
5096+
// FIXME: Support FP.
5097+
return !Op.getOperand(0).getValueType().isInteger();
5098+
50935099
// Matches hasPoisonGeneratingFlags().
50945100
case ISD::ZERO_EXTEND:
50955101
return ConsiderFlags && Op->getFlags().hasNonNeg();

‎llvm/test/CodeGen/RISCV/alu64.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,8 @@ define i64 @sltiu(i64 %a) nounwind {
5757
;
5858
; RV32I-LABEL: sltiu:
5959
; RV32I: # %bb.0:
60+
; RV32I-NEXT: seqz a1, a1
6061
; RV32I-NEXT: sltiu a0, a0, 3
61-
; RV32I-NEXT: snez a1, a1
62-
; RV32I-NEXT: addi a1, a1, -1
6362
; RV32I-NEXT: and a0, a1, a0
6463
; RV32I-NEXT: li a1, 0
6564
; RV32I-NEXT: ret

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 21 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -868,32 +868,33 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
868868
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
869869
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
870870
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
871+
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
871872
; RV32I-NEXT: mv s0, a1
872873
; RV32I-NEXT: mv s1, a0
873-
; RV32I-NEXT: lui a3, 278016
874-
; RV32I-NEXT: addi a3, a3, -1
875-
; RV32I-NEXT: li a2, -1
876-
; RV32I-NEXT: call __gtdf2
877-
; RV32I-NEXT: mv s2, a0
878874
; RV32I-NEXT: lui a3, 802304
879-
; RV32I-NEXT: mv a0, s1
880-
; RV32I-NEXT: mv a1, s0
881875
; RV32I-NEXT: li a2, 0
882876
; RV32I-NEXT: call __gedf2
883-
; RV32I-NEXT: mv s3, a0
877+
; RV32I-NEXT: mv s2, a0
884878
; RV32I-NEXT: mv a0, s1
885879
; RV32I-NEXT: mv a1, s0
886880
; RV32I-NEXT: call __fixdfdi
887-
; RV32I-NEXT: mv s4, a0
888-
; RV32I-NEXT: mv s5, a1
889-
; RV32I-NEXT: lui a0, 524288
890-
; RV32I-NEXT: bgez s3, .LBB12_2
881+
; RV32I-NEXT: mv s3, a0
882+
; RV32I-NEXT: mv s4, a1
883+
; RV32I-NEXT: lui s6, 524288
884+
; RV32I-NEXT: bgez s2, .LBB12_2
891885
; RV32I-NEXT: # %bb.1: # %start
892-
; RV32I-NEXT: lui s5, 524288
886+
; RV32I-NEXT: lui s4, 524288
893887
; RV32I-NEXT: .LBB12_2: # %start
894-
; RV32I-NEXT: blez s2, .LBB12_4
888+
; RV32I-NEXT: lui a3, 278016
889+
; RV32I-NEXT: addi a3, a3, -1
890+
; RV32I-NEXT: li a2, -1
891+
; RV32I-NEXT: mv a0, s1
892+
; RV32I-NEXT: mv a1, s0
893+
; RV32I-NEXT: call __gtdf2
894+
; RV32I-NEXT: mv s5, a0
895+
; RV32I-NEXT: blez a0, .LBB12_4
895896
; RV32I-NEXT: # %bb.3: # %start
896-
; RV32I-NEXT: addi s5, a0, -1
897+
; RV32I-NEXT: addi s4, s6, -1
897898
; RV32I-NEXT: .LBB12_4: # %start
898899
; RV32I-NEXT: mv a0, s1
899900
; RV32I-NEXT: mv a1, s0
@@ -902,11 +903,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
902903
; RV32I-NEXT: call __unorddf2
903904
; RV32I-NEXT: snez a0, a0
904905
; RV32I-NEXT: addi a0, a0, -1
905-
; RV32I-NEXT: and a1, a0, s5
906-
; RV32I-NEXT: slti a2, s3, 0
906+
; RV32I-NEXT: and a1, a0, s4
907+
; RV32I-NEXT: slti a2, s2, 0
907908
; RV32I-NEXT: addi a2, a2, -1
908-
; RV32I-NEXT: and a2, a2, s4
909-
; RV32I-NEXT: sgtz a3, s2
909+
; RV32I-NEXT: and a2, a2, s3
910+
; RV32I-NEXT: sgtz a3, s5
910911
; RV32I-NEXT: neg a3, a3
911912
; RV32I-NEXT: or a2, a3, a2
912913
; RV32I-NEXT: and a0, a0, a2
@@ -917,6 +918,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
917918
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
918919
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
919920
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
921+
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
920922
; RV32I-NEXT: addi sp, sp, 32
921923
; RV32I-NEXT: ret
922924
;

‎llvm/test/CodeGen/RISCV/forced-atomics.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3659,8 +3659,8 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
36593659
; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1
36603660
; RV32-NEXT: neg a3, a0
36613661
; RV32-NEXT: and a3, a3, a1
3662-
; RV32-NEXT: sw a4, 0(sp)
36633662
; RV32-NEXT: sw a1, 4(sp)
3663+
; RV32-NEXT: sw a4, 0(sp)
36643664
; RV32-NEXT: mv a1, sp
36653665
; RV32-NEXT: li a4, 5
36663666
; RV32-NEXT: li a5, 5
@@ -3672,8 +3672,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
36723672
; RV32-NEXT: .LBB52_2: # %atomicrmw.start
36733673
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
36743674
; RV32-NEXT: sltiu a0, a4, 2
3675-
; RV32-NEXT: snez a2, a1
3676-
; RV32-NEXT: addi a2, a2, -1
3675+
; RV32-NEXT: seqz a2, a1
36773676
; RV32-NEXT: and a0, a2, a0
36783677
; RV32-NEXT: mv a2, a4
36793678
; RV32-NEXT: bnez a0, .LBB52_1

‎llvm/test/CodeGen/RISCV/fpclamptosat.ll

Lines changed: 18 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -114,9 +114,8 @@ define i32 @utest_f64i32(double %x) {
114114
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
115115
; RV32IF-NEXT: .cfi_offset ra, -4
116116
; RV32IF-NEXT: call __fixunsdfdi
117+
; RV32IF-NEXT: seqz a1, a1
117118
; RV32IF-NEXT: sltiu a2, a0, -1
118-
; RV32IF-NEXT: snez a1, a1
119-
; RV32IF-NEXT: addi a1, a1, -1
120119
; RV32IF-NEXT: and a1, a1, a2
121120
; RV32IF-NEXT: addi a1, a1, -1
122121
; RV32IF-NEXT: or a0, a1, a0
@@ -430,9 +429,8 @@ define i32 @utesth_f16i32(half %x) {
430429
; RV32-NEXT: .cfi_offset ra, -4
431430
; RV32-NEXT: call __extendhfsf2
432431
; RV32-NEXT: call __fixunssfdi
432+
; RV32-NEXT: seqz a1, a1
433433
; RV32-NEXT: sltiu a2, a0, -1
434-
; RV32-NEXT: snez a1, a1
435-
; RV32-NEXT: addi a1, a1, -1
436434
; RV32-NEXT: and a1, a1, a2
437435
; RV32-NEXT: addi a1, a1, -1
438436
; RV32-NEXT: or a0, a1, a0
@@ -1229,10 +1227,8 @@ define i64 @utest_f64i64(double %x) {
12291227
; RV32IF-NEXT: lw a1, 20(sp)
12301228
; RV32IF-NEXT: lw a2, 12(sp)
12311229
; RV32IF-NEXT: lw a3, 8(sp)
1232-
; RV32IF-NEXT: seqz a4, a0
1233-
; RV32IF-NEXT: snez a5, a1
1234-
; RV32IF-NEXT: addi a5, a5, -1
1235-
; RV32IF-NEXT: and a4, a5, a4
1230+
; RV32IF-NEXT: or a4, a1, a0
1231+
; RV32IF-NEXT: seqz a4, a4
12361232
; RV32IF-NEXT: xori a0, a0, 1
12371233
; RV32IF-NEXT: or a0, a0, a1
12381234
; RV32IF-NEXT: seqz a0, a0
@@ -1271,10 +1267,8 @@ define i64 @utest_f64i64(double %x) {
12711267
; RV32IFD-NEXT: lw a1, 20(sp)
12721268
; RV32IFD-NEXT: lw a2, 12(sp)
12731269
; RV32IFD-NEXT: lw a3, 8(sp)
1274-
; RV32IFD-NEXT: seqz a4, a0
1275-
; RV32IFD-NEXT: snez a5, a1
1276-
; RV32IFD-NEXT: addi a5, a5, -1
1277-
; RV32IFD-NEXT: and a4, a5, a4
1270+
; RV32IFD-NEXT: or a4, a1, a0
1271+
; RV32IFD-NEXT: seqz a4, a4
12781272
; RV32IFD-NEXT: xori a0, a0, 1
12791273
; RV32IFD-NEXT: or a0, a0, a1
12801274
; RV32IFD-NEXT: seqz a0, a0
@@ -1531,10 +1525,8 @@ define i64 @utest_f32i64(float %x) {
15311525
; RV32-NEXT: lw a1, 20(sp)
15321526
; RV32-NEXT: lw a2, 12(sp)
15331527
; RV32-NEXT: lw a3, 8(sp)
1534-
; RV32-NEXT: seqz a4, a0
1535-
; RV32-NEXT: snez a5, a1
1536-
; RV32-NEXT: addi a5, a5, -1
1537-
; RV32-NEXT: and a4, a5, a4
1528+
; RV32-NEXT: or a4, a1, a0
1529+
; RV32-NEXT: seqz a4, a4
15381530
; RV32-NEXT: xori a0, a0, 1
15391531
; RV32-NEXT: or a0, a0, a1
15401532
; RV32-NEXT: seqz a0, a0
@@ -1783,10 +1775,8 @@ define i64 @utesth_f16i64(half %x) {
17831775
; RV32-NEXT: lw a1, 20(sp)
17841776
; RV32-NEXT: lw a2, 12(sp)
17851777
; RV32-NEXT: lw a3, 8(sp)
1786-
; RV32-NEXT: seqz a4, a0
1787-
; RV32-NEXT: snez a5, a1
1788-
; RV32-NEXT: addi a5, a5, -1
1789-
; RV32-NEXT: and a4, a5, a4
1778+
; RV32-NEXT: or a4, a1, a0
1779+
; RV32-NEXT: seqz a4, a4
17901780
; RV32-NEXT: xori a0, a0, 1
17911781
; RV32-NEXT: or a0, a0, a1
17921782
; RV32-NEXT: seqz a0, a0
@@ -3087,10 +3077,8 @@ define i64 @utest_f64i64_mm(double %x) {
30873077
; RV32IF-NEXT: lw a1, 20(sp)
30883078
; RV32IF-NEXT: lw a2, 12(sp)
30893079
; RV32IF-NEXT: lw a3, 8(sp)
3090-
; RV32IF-NEXT: seqz a4, a0
3091-
; RV32IF-NEXT: snez a5, a1
3092-
; RV32IF-NEXT: addi a5, a5, -1
3093-
; RV32IF-NEXT: and a4, a5, a4
3080+
; RV32IF-NEXT: or a4, a1, a0
3081+
; RV32IF-NEXT: seqz a4, a4
30943082
; RV32IF-NEXT: xori a0, a0, 1
30953083
; RV32IF-NEXT: or a0, a0, a1
30963084
; RV32IF-NEXT: seqz a0, a0
@@ -3129,10 +3117,8 @@ define i64 @utest_f64i64_mm(double %x) {
31293117
; RV32IFD-NEXT: lw a1, 20(sp)
31303118
; RV32IFD-NEXT: lw a2, 12(sp)
31313119
; RV32IFD-NEXT: lw a3, 8(sp)
3132-
; RV32IFD-NEXT: seqz a4, a0
3133-
; RV32IFD-NEXT: snez a5, a1
3134-
; RV32IFD-NEXT: addi a5, a5, -1
3135-
; RV32IFD-NEXT: and a4, a5, a4
3120+
; RV32IFD-NEXT: or a4, a1, a0
3121+
; RV32IFD-NEXT: seqz a4, a4
31363122
; RV32IFD-NEXT: xori a0, a0, 1
31373123
; RV32IFD-NEXT: or a0, a0, a1
31383124
; RV32IFD-NEXT: seqz a0, a0
@@ -3345,10 +3331,8 @@ define i64 @utest_f32i64_mm(float %x) {
33453331
; RV32-NEXT: lw a1, 20(sp)
33463332
; RV32-NEXT: lw a2, 12(sp)
33473333
; RV32-NEXT: lw a3, 8(sp)
3348-
; RV32-NEXT: seqz a4, a0
3349-
; RV32-NEXT: snez a5, a1
3350-
; RV32-NEXT: addi a5, a5, -1
3351-
; RV32-NEXT: and a4, a5, a4
3334+
; RV32-NEXT: or a4, a1, a0
3335+
; RV32-NEXT: seqz a4, a4
33523336
; RV32-NEXT: xori a0, a0, 1
33533337
; RV32-NEXT: or a0, a0, a1
33543338
; RV32-NEXT: seqz a0, a0
@@ -3570,10 +3554,8 @@ define i64 @utesth_f16i64_mm(half %x) {
35703554
; RV32-NEXT: lw a1, 20(sp)
35713555
; RV32-NEXT: lw a2, 12(sp)
35723556
; RV32-NEXT: lw a3, 8(sp)
3573-
; RV32-NEXT: seqz a4, a0
3574-
; RV32-NEXT: snez a5, a1
3575-
; RV32-NEXT: addi a5, a5, -1
3576-
; RV32-NEXT: and a4, a5, a4
3557+
; RV32-NEXT: or a4, a1, a0
3558+
; RV32-NEXT: seqz a4, a4
35773559
; RV32-NEXT: xori a0, a0, 1
35783560
; RV32-NEXT: or a0, a0, a1
35793561
; RV32-NEXT: seqz a0, a0

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