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‎llvm/test/CodeGen/AArch64/cmp-chains.ll

Lines changed: 154 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,3 +258,157 @@ define i32 @neg_range_int(i32 %a, i32 %b, i32 %c) {
258258
ret i32 %retval.0
259259
}
260260

261+
; (b > -(d | 1) && a < c)
262+
define i32 @neg_range_int_comp(i32 %a, i32 %b, i32 %c, i32 %d) {
263+
; CHECK-LABEL: neg_range_int_comp:
264+
; CHECK: // %bb.0:
265+
; CHECK-NEXT: orr w8, w3, #0x1
266+
; CHECK-NEXT: cmp w0, w2
267+
; CHECK-NEXT: neg w8, w8
268+
; CHECK-NEXT: ccmp w1, w8, #4, lt
269+
; CHECK-NEXT: csel w0, w1, w0, gt
270+
; CHECK-NEXT: ret
271+
%dor = or i32 %d, 1
272+
%negd = sub i32 0, %dor
273+
%cmp = icmp sgt i32 %b, %negd
274+
%cmp1 = icmp slt i32 %a, %c
275+
%or.cond = and i1 %cmp, %cmp1
276+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
277+
ret i32 %retval.0
278+
}
279+
280+
; (b >u -(d | 1) && a < c)
281+
define i32 @neg_range_int_comp_u(i32 %a, i32 %b, i32 %c, i32 %d) {
282+
; CHECK-LABEL: neg_range_int_comp_u:
283+
; CHECK: // %bb.0:
284+
; CHECK-NEXT: orr w8, w3, #0x1
285+
; CHECK-NEXT: cmp w0, w2
286+
; CHECK-NEXT: neg w8, w8
287+
; CHECK-NEXT: ccmp w1, w8, #0, lt
288+
; CHECK-NEXT: csel w0, w1, w0, hi
289+
; CHECK-NEXT: ret
290+
%dor = or i32 %d, 1
291+
%negd = sub i32 0, %dor
292+
%cmp = icmp ugt i32 %b, %negd
293+
%cmp1 = icmp slt i32 %a, %c
294+
%or.cond = and i1 %cmp, %cmp1
295+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
296+
ret i32 %retval.0
297+
}
298+
299+
; (b > -(d | 1) && a u < c)
300+
define i32 @neg_range_int_comp_ua(i32 %a, i32 %b, i32 %c, i32 %d) {
301+
; CHECK-LABEL: neg_range_int_comp_ua:
302+
; CHECK: // %bb.0:
303+
; CHECK-NEXT: orr w8, w3, #0x1
304+
; CHECK-NEXT: cmp w0, w2
305+
; CHECK-NEXT: neg w8, w8
306+
; CHECK-NEXT: ccmp w1, w8, #4, lo
307+
; CHECK-NEXT: csel w0, w1, w0, gt
308+
; CHECK-NEXT: ret
309+
%dor = or i32 %d, 1
310+
%negd = sub i32 0, %dor
311+
%cmp = icmp sgt i32 %b, %negd
312+
%cmp1 = icmp ult i32 %a, %c
313+
%or.cond = and i1 %cmp, %cmp1
314+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
315+
ret i32 %retval.0
316+
}
317+
318+
; (b <= -3 && a > c)
319+
define i32 @neg_range_int_2(i32 %a, i32 %b, i32 %c) {
320+
; SDISEL-LABEL: neg_range_int_2:
321+
; SDISEL: // %bb.0:
322+
; SDISEL-NEXT: cmp w0, w2
323+
; SDISEL-NEXT: ccmn w1, #4, #4, gt
324+
; SDISEL-NEXT: csel w0, w1, w0, gt
325+
; SDISEL-NEXT: ret
326+
;
327+
; GISEL-LABEL: neg_range_int_2:
328+
; GISEL: // %bb.0:
329+
; GISEL-NEXT: cmp w0, w2
330+
; GISEL-NEXT: ccmn w1, #3, #8, gt
331+
; GISEL-NEXT: csel w0, w1, w0, ge
332+
; GISEL-NEXT: ret
333+
%cmp = icmp sge i32 %b, -3
334+
%cmp1 = icmp sgt i32 %a, %c
335+
%or.cond = and i1 %cmp, %cmp1
336+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
337+
ret i32 %retval.0
338+
}
339+
340+
; (b < -(d | 1) && a >= c)
341+
define i32 @neg_range_int_comp2(i32 %a, i32 %b, i32 %c, i32 %d) {
342+
; CHECK-LABEL: neg_range_int_comp2:
343+
; CHECK: // %bb.0:
344+
; CHECK-NEXT: orr w8, w3, #0x1
345+
; CHECK-NEXT: cmp w0, w2
346+
; CHECK-NEXT: neg w8, w8
347+
; CHECK-NEXT: ccmp w1, w8, #0, ge
348+
; CHECK-NEXT: csel w0, w1, w0, lt
349+
; CHECK-NEXT: ret
350+
%dor = or i32 %d, 1
351+
%negd = sub i32 0, %dor
352+
%cmp = icmp slt i32 %b, %negd
353+
%cmp1 = icmp sge i32 %a, %c
354+
%or.cond = and i1 %cmp, %cmp1
355+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
356+
ret i32 %retval.0
357+
}
358+
359+
; (b <u -(d | 1) && a > c)
360+
define i32 @neg_range_int_comp_u2(i32 %a, i32 %b, i32 %c, i32 %d) {
361+
; CHECK-LABEL: neg_range_int_comp_u2:
362+
; CHECK: // %bb.0:
363+
; CHECK-NEXT: orr w8, w3, #0x1
364+
; CHECK-NEXT: cmp w0, w2
365+
; CHECK-NEXT: neg w8, w8
366+
; CHECK-NEXT: ccmp w1, w8, #2, gt
367+
; CHECK-NEXT: csel w0, w1, w0, lo
368+
; CHECK-NEXT: ret
369+
%dor = or i32 %d, 1
370+
%negd = sub i32 0, %dor
371+
%cmp = icmp ult i32 %b, %negd
372+
%cmp1 = icmp sgt i32 %a, %c
373+
%or.cond = and i1 %cmp, %cmp1
374+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
375+
ret i32 %retval.0
376+
}
377+
378+
; (b > -(d | 1) && a u > c)
379+
define i32 @neg_range_int_comp_ua2(i32 %a, i32 %b, i32 %c, i32 %d) {
380+
; CHECK-LABEL: neg_range_int_comp_ua2:
381+
; CHECK: // %bb.0:
382+
; CHECK-NEXT: orr w8, w3, #0x1
383+
; CHECK-NEXT: cmp w0, w2
384+
; CHECK-NEXT: neg w8, w8
385+
; CHECK-NEXT: ccmp w1, w8, #4, hi
386+
; CHECK-NEXT: csel w0, w1, w0, gt
387+
; CHECK-NEXT: ret
388+
%dor = or i32 %d, 1
389+
%negd = sub i32 0, %dor
390+
%cmp = icmp sgt i32 %b, %negd
391+
%cmp1 = icmp ugt i32 %a, %c
392+
%or.cond = and i1 %cmp, %cmp1
393+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
394+
ret i32 %retval.0
395+
}
396+
397+
; (b > -(d | 1) && a u == c)
398+
define i32 @neg_range_int_comp_ua3(i32 %a, i32 %b, i32 %c, i32 %d) {
399+
; CHECK-LABEL: neg_range_int_comp_ua3:
400+
; CHECK: // %bb.0:
401+
; CHECK-NEXT: orr w8, w3, #0x1
402+
; CHECK-NEXT: cmp w0, w2
403+
; CHECK-NEXT: neg w8, w8
404+
; CHECK-NEXT: ccmp w1, w8, #4, eq
405+
; CHECK-NEXT: csel w0, w1, w0, gt
406+
; CHECK-NEXT: ret
407+
%dor = or i32 %d, 1
408+
%negd = sub i32 0, %dor
409+
%cmp = icmp sgt i32 %b, %negd
410+
%cmp1 = icmp eq i32 %a, %c
411+
%or.cond = and i1 %cmp, %cmp1
412+
%retval.0 = select i1 %or.cond, i32 %b, i32 %a
413+
ret i32 %retval.0
414+
}

‎llvm/test/CodeGen/AArch64/cmp-select-sign.ll

Lines changed: 214 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -262,4 +262,218 @@ define <4 x i65> @sign_4xi65(<4 x i65> %a) {
262262
ret <4 x i65> %res
263263
}
264264

265+
define i32 @or_neg(i32 %x, i32 %y) {
266+
; CHECK-LABEL: or_neg:
267+
; CHECK: // %bb.0:
268+
; CHECK-NEXT: orr w8, w0, #0x1
269+
; CHECK-NEXT: neg w8, w8
270+
; CHECK-NEXT: cmp w8, w1
271+
; CHECK-NEXT: cset w0, gt
272+
; CHECK-NEXT: ret
273+
%3 = or i32 %x, 1
274+
%4 = sub i32 0, %3
275+
%5 = icmp sgt i32 %4, %y
276+
%6 = zext i1 %5 to i32
277+
ret i32 %6
278+
}
279+
280+
define i32 @or_neg_ugt(i32 %x, i32 %y) {
281+
; CHECK-LABEL: or_neg_ugt:
282+
; CHECK: // %bb.0:
283+
; CHECK-NEXT: orr w8, w0, #0x1
284+
; CHECK-NEXT: neg w8, w8
285+
; CHECK-NEXT: cmp w8, w1
286+
; CHECK-NEXT: cset w0, hi
287+
; CHECK-NEXT: ret
288+
%3 = or i32 %x, 1
289+
%4 = sub i32 0, %3
290+
%5 = icmp ugt i32 %4, %y
291+
%6 = zext i1 %5 to i32
292+
ret i32 %6
293+
}
294+
295+
; Negative test
296+
297+
define i32 @or_neg_no_smin(i32 %x, i32 %y) {
298+
; CHECK-LABEL: or_neg_no_smin:
299+
; CHECK: // %bb.0:
300+
; CHECK-NEXT: neg w8, w0
301+
; CHECK-NEXT: cmp w8, w1
302+
; CHECK-NEXT: cset w0, gt
303+
; CHECK-NEXT: ret
304+
%4 = sub i32 0, %x
305+
%5 = icmp sgt i32 %4, %y
306+
%6 = zext i1 %5 to i32
307+
ret i32 %6
308+
}
309+
310+
; Negative test
311+
312+
define i32 @or_neg_ult_no_zero(i32 %x, i32 %y) {
313+
; CHECK-LABEL: or_neg_ult_no_zero:
314+
; CHECK: // %bb.0:
315+
; CHECK-NEXT: neg w8, w0
316+
; CHECK-NEXT: cmp w8, w1
317+
; CHECK-NEXT: cset w0, lo
318+
; CHECK-NEXT: ret
319+
%4 = sub i32 0, %x
320+
%5 = icmp ult i32 %4, %y
321+
%6 = zext i1 %5 to i32
322+
ret i32 %6
323+
}
324+
325+
define i32 @or_neg_no_smin_but_zero(i32 %x, i32 %y) {
326+
; CHECK-LABEL: or_neg_no_smin_but_zero:
327+
; CHECK: // %bb.0:
328+
; CHECK-NEXT: bic w8, w0, w0, asr #31
329+
; CHECK-NEXT: neg w8, w8
330+
; CHECK-NEXT: cmp w8, w1
331+
; CHECK-NEXT: cset w0, gt
332+
; CHECK-NEXT: ret
333+
%3 = call i32 @llvm.smax.i32(i32 %x, i32 0)
334+
%4 = sub i32 0, %3
335+
%5 = icmp sgt i32 %4, %y
336+
%6 = zext i1 %5 to i32
337+
ret i32 %6
338+
}
339+
340+
define i32 @or_neg_slt_zero_but_no_smin(i32 %x, i32 %y) {
341+
; CHECK-LABEL: or_neg_slt_zero_but_no_smin:
342+
; CHECK: // %bb.0:
343+
; CHECK-NEXT: mov w8, #9 // =0x9
344+
; CHECK-NEXT: cmp w0, #9
345+
; CHECK-NEXT: csel w8, w0, w8, lo
346+
; CHECK-NEXT: neg w8, w8
347+
; CHECK-NEXT: cmp w8, w1
348+
; CHECK-NEXT: cset w0, hi
349+
; CHECK-NEXT: ret
350+
%3 = call i32 @llvm.umin.i32(i32 %x, i32 9)
351+
%4 = sub i32 0, %3
352+
%5 = icmp ugt i32 %4, %y
353+
%6 = zext i1 %5 to i32
354+
ret i32 %6
355+
}
356+
357+
define i32 @or_neg2(i32 %x, i32 %y) {
358+
; CHECK-LABEL: or_neg2:
359+
; CHECK: // %bb.0:
360+
; CHECK-NEXT: orr w8, w0, #0x1
361+
; CHECK-NEXT: neg w8, w8
362+
; CHECK-NEXT: cmp w8, w1
363+
; CHECK-NEXT: cset w0, ge
364+
; CHECK-NEXT: ret
365+
%3 = or i32 %x, 1
366+
%4 = sub i32 0, %3
367+
%5 = icmp sge i32 %4, %y
368+
%6 = zext i1 %5 to i32
369+
ret i32 %6
370+
}
371+
372+
define i32 @or_neg3(i32 %x, i32 %y) {
373+
; CHECK-LABEL: or_neg3:
374+
; CHECK: // %bb.0:
375+
; CHECK-NEXT: orr w8, w0, #0x1
376+
; CHECK-NEXT: neg w8, w8
377+
; CHECK-NEXT: cmp w8, w1
378+
; CHECK-NEXT: cset w0, lt
379+
; CHECK-NEXT: ret
380+
%3 = or i32 %x, 1
381+
%4 = sub i32 0, %3
382+
%5 = icmp slt i32 %4, %y
383+
%6 = zext i1 %5 to i32
384+
ret i32 %6
385+
}
386+
387+
define i32 @or_neg4(i32 %x, i32 %y) {
388+
; CHECK-LABEL: or_neg4:
389+
; CHECK: // %bb.0:
390+
; CHECK-NEXT: orr w8, w0, #0x1
391+
; CHECK-NEXT: neg w8, w8
392+
; CHECK-NEXT: cmp w8, w1
393+
; CHECK-NEXT: cset w0, le
394+
; CHECK-NEXT: ret
395+
%3 = or i32 %x, 1
396+
%4 = sub i32 0, %3
397+
%5 = icmp sle i32 %4, %y
398+
%6 = zext i1 %5 to i32
399+
ret i32 %6
400+
}
401+
402+
define i32 @or_neg_ult(i32 %x, i32 %y) {
403+
; CHECK-LABEL: or_neg_ult:
404+
; CHECK: // %bb.0:
405+
; CHECK-NEXT: orr w8, w0, #0x1
406+
; CHECK-NEXT: neg w8, w8
407+
; CHECK-NEXT: cmp w8, w1
408+
; CHECK-NEXT: cset w0, hi
409+
; CHECK-NEXT: ret
410+
%3 = or i32 %x, 1
411+
%4 = sub i32 0, %3
412+
%5 = icmp ugt i32 %4, %y
413+
%6 = zext i1 %5 to i32
414+
ret i32 %6
415+
}
416+
417+
define i32 @or_neg_no_smin2(i32 %x, i32 %y) {
418+
; CHECK-LABEL: or_neg_no_smin2:
419+
; CHECK: // %bb.0:
420+
; CHECK-NEXT: neg w8, w0
421+
; CHECK-NEXT: cmp w8, w1
422+
; CHECK-NEXT: cset w0, ge
423+
; CHECK-NEXT: ret
424+
%4 = sub i32 0, %x
425+
%5 = icmp sge i32 %4, %y
426+
%6 = zext i1 %5 to i32
427+
ret i32 %6
428+
}
429+
430+
; Negative test
431+
432+
define i32 @or_neg_ult_no_zero2(i32 %x, i32 %y) {
433+
; CHECK-LABEL: or_neg_ult_no_zero2:
434+
; CHECK: // %bb.0:
435+
; CHECK-NEXT: neg w8, w0
436+
; CHECK-NEXT: cmp w8, w1
437+
; CHECK-NEXT: cset w0, lo
438+
; CHECK-NEXT: ret
439+
%4 = sub i32 0, %x
440+
%5 = icmp ult i32 %4, %y
441+
%6 = zext i1 %5 to i32
442+
ret i32 %6
443+
}
444+
445+
define i32 @or_neg_no_smin_but_zero2(i32 %x, i32 %y) {
446+
; CHECK-LABEL: or_neg_no_smin_but_zero2:
447+
; CHECK: // %bb.0:
448+
; CHECK-NEXT: bic w8, w0, w0, asr #31
449+
; CHECK-NEXT: neg w8, w8
450+
; CHECK-NEXT: cmp w8, w1
451+
; CHECK-NEXT: cset w0, le
452+
; CHECK-NEXT: ret
453+
%3 = call i32 @llvm.smax.i32(i32 %x, i32 0)
454+
%4 = sub i32 0, %3
455+
%5 = icmp sle i32 %4, %y
456+
%6 = zext i1 %5 to i32
457+
ret i32 %6
458+
}
459+
460+
define i32 @or_neg_slt_zero_but_no_smin2(i32 %x, i32 %y) {
461+
; CHECK-LABEL: or_neg_slt_zero_but_no_smin2:
462+
; CHECK: // %bb.0:
463+
; CHECK-NEXT: mov w8, #9 // =0x9
464+
; CHECK-NEXT: cmp w0, #9
465+
; CHECK-NEXT: csel w8, w0, w8, lo
466+
; CHECK-NEXT: neg w8, w8
467+
; CHECK-NEXT: cmp w8, w1
468+
; CHECK-NEXT: cset w0, hs
469+
; CHECK-NEXT: ret
470+
%3 = call i32 @llvm.umin.i32(i32 %x, i32 9)
471+
%4 = sub i32 0, %3
472+
%5 = icmp uge i32 %4, %y
473+
%6 = zext i1 %5 to i32
474+
ret i32 %6
475+
}
476+
477+
declare i32 @llvm.smax.i32(i32, i32)
478+
declare i32 @llvm.umax.i32(i32, i32)
265479
declare void @use_4xi1(<4 x i1>)

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