[DebugInfo] Store instr-ref mode of MachineFunction in member

Add a flag state (and a MIR key) to MachineFunctions indicating whether they
contain instruction referencing debug-info or not. Whether DBG_VALUEs or
DBG_INSTR_REFs are used needs to be determined by LiveDebugValues at least, and
using the current optimisation level as a proxy is proving unreliable.

Test updates are purely adding the flag to tests, in a couple of cases it
involves separating out VarLocBasedLDV/InstrRefBasedLDV tests into separate
files, as they can no longer share the same input.

Differential Revision: https://reviews.llvm.org/D141387

Author: jmorse

llvm/include/llvm/CodeGen/FastISel.h

@@ -213,7 +213,6 @@ class FastISel {
   const TargetRegisterInfo &TRI;
   const TargetLibraryInfo *LibInfo;
   bool SkipTargetIndependentISel;
-  bool UseInstrRefDebugInfo = false;
 
   /// The position of the last instruction for materializing constants
   /// for use in the current block. It resets to EmitStartPt when it makes sense
@@ -320,12 +319,6 @@ class FastISel {
   /// Reset InsertPt to the given old insert position.
   void leaveLocalValueArea(SavePoint Old);
 
-  /// Signal whether instruction referencing variable locations are desired for
-  /// this function's debug-info.
-  void useInstrRefDebugInfo(bool Flag) {
-    UseInstrRefDebugInfo = Flag;
-  }
-
 protected:
   explicit FastISel(FunctionLoweringInfo &FuncInfo,
                     const TargetLibraryInfo *LibInfo,

llvm/include/llvm/CodeGen/MIRYamlMapping.h

@@ -707,6 +707,7 @@ struct MachineFunction {
 
   bool FailsVerification = false;
   bool TracksDebugUserValues = false;
+  bool UseDebugInstrRef = false;
   std::vector<VirtualRegisterDefinition> VirtualRegisters;
   std::vector<MachineFunctionLiveIn> LiveIns;
   std::optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
@@ -741,6 +742,7 @@ template <> struct MappingTraits<MachineFunction> {
     YamlIO.mapOptional("hasEHCatchret", MF.HasEHCatchret, false);
     YamlIO.mapOptional("hasEHScopes", MF.HasEHScopes, false);
     YamlIO.mapOptional("hasEHFunclets", MF.HasEHFunclets, false);
+    YamlIO.mapOptional("debugInstrRef", MF.UseDebugInstrRef, false);
 
     YamlIO.mapOptional("failsVerification", MF.FailsVerification, false);
     YamlIO.mapOptional("tracksDebugUserValues", MF.TracksDebugUserValues,

llvm/include/llvm/CodeGen/MachineFunction.h

@@ -527,6 +527,10 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   /// during register allocation. See DebugPHIRegallocPos.
   DenseMap<unsigned, DebugPHIRegallocPos> DebugPHIPositions;
 
+  /// Flag for whether this function contains DBG_VALUEs (false) or
+  /// DBG_INSTR_REF (true).
+  bool UseDebugInstrRef = false;
+
   /// Create a substitution between one <instr,operand> value to a different,
   /// new value.
   void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair,
@@ -567,10 +571,17 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
   /// (or DBG_PHI).
   void finalizeDebugInstrRefs();
 
-  /// Returns true if the function's variable locations should be tracked with
+  /// Determine whether, in the current machine configuration, we should use
+  /// instruction referencing or not.
+  bool shouldUseDebugInstrRef() const;
+
+  /// Returns true if the function's variable locations are tracked with
   /// instruction referencing.
   bool useDebugInstrRef() const;
 
+  /// Set whether this function will use instruction referencing or not.
+  void setUseDebugInstrRef(bool UseInstrRef);
+
   /// A reserved operand number representing the instructions memory operand,
   /// for instructions that have a stack spill fused into them.
   const static unsigned int DebugOperandMemNumber;

llvm/include/llvm/CodeGen/SelectionDAG.h

@@ -293,9 +293,6 @@ class SelectionDAG {
   /// benefits (see discussion with @thakis in D120714).
   uint16_t NextPersistentId = 0;
 
-  /// Are instruction referencing variable locations desired for this function?
-  bool UseInstrRefDebugInfo = false;
-
 public:
   /// Clients of various APIs that cause global effects on
   /// the DAG can optionally implement this interface.  This allows the clients
@@ -1901,16 +1898,6 @@ class SelectionDAG {
   /// function mirrors \c llvm::salvageDebugInfo.
   void salvageDebugInfo(SDNode &N);
 
-  /// Signal whether instruction referencing variable locations are desired for
-  /// this function's debug-info.
-  void useInstrRefDebugInfo(bool Flag) {
-    UseInstrRefDebugInfo = Flag;
-  }
-
-  bool getUseInstrRefDebugInfo() const {
-    return UseInstrRefDebugInfo;
-  }
-
   void dump() const;
 
   /// In most cases this function returns the ABI alignment for a given type,

llvm/include/llvm/CodeGen/SelectionDAGISel.h

@@ -56,7 +56,6 @@ class SelectionDAGISel : public MachineFunctionPass {
   const TargetLowering *TLI;
   bool FastISelFailed;
   SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
-  bool UseInstrRefDebugInfo = false;
 
   /// Current optimization remark emitter.
   /// Used to report things like combines and FastISel failures.

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -443,6 +443,9 @@ void MIRParserImpl::setupDebugValueTracking(
     MF.makeDebugValueSubstitution({Sub.SrcInst, Sub.SrcOp},
                                   {Sub.DstInst, Sub.DstOp}, Sub.Subreg);
   }
+
+  // Flag for whether we're supposed to be using DBG_INSTR_REF.
+  MF.setUseDebugInstrRef(YamlMF.UseDebugInstrRef);
 }
 
 bool

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -200,6 +200,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
   YamlMF.HasEHCatchret = MF.hasEHCatchret();
   YamlMF.HasEHScopes = MF.hasEHScopes();
   YamlMF.HasEHFunclets = MF.hasEHFunclets();
+  YamlMF.UseDebugInstrRef = MF.useDebugInstrRef();
 
   YamlMF.Legalized = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Legalized);

llvm/lib/CodeGen/MachineFunction.cpp

@@ -1195,7 +1195,7 @@ void MachineFunction::finalizeDebugInstrRefs() {
   }
 }
 
-bool MachineFunction::useDebugInstrRef() const {
+bool MachineFunction::shouldUseDebugInstrRef() const {
   // Disable instr-ref at -O0: it's very slow (in compile time). We can still
   // have optimized code inlined into this unoptimized code, however with
   // fewer and less aggressive optimizations happening, coverage and accuracy
@@ -1213,6 +1213,14 @@ bool MachineFunction::useDebugInstrRef() const {
   return false;
 }
 
+bool MachineFunction::useDebugInstrRef() const {
+  return UseDebugInstrRef;
+}
+
+void MachineFunction::setUseDebugInstrRef(bool Use) {
+  UseDebugInstrRef = Use;
+}
+
 // Use one million as a high / reserved number.
 const unsigned MachineFunction::DebugOperandMemNumber = 1000000;
 

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

@@ -1247,7 +1247,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
     if (Op) {
       assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
              "Expected inlined-at fields to agree");
-      if (UseInstrRefDebugInfo && Op->isReg()) {
+      if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) {
         // If using instruction referencing, produce this as a DBG_INSTR_REF,
         // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
         // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
@@ -1309,7 +1309,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
           .addMetadata(DI->getExpression());
     } else if (Register Reg = lookUpRegForValue(V)) {
       // FIXME: This does not handle register-indirect values at offset 0.
-      if (!UseInstrRefDebugInfo) {
+      if (!FuncInfo.MF->useDebugInstrRef()) {
         bool IsIndirect = false;
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II, IsIndirect,
                 Reg, DI->getVariable(), DI->getExpression());

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

@@ -1395,12 +1395,11 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
 /// at the given position in the given block.
 InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
-                           MachineBasicBlock::iterator insertpos,
-                           bool UseInstrRefDebugInfo)
+                           MachineBasicBlock::iterator insertpos)
     : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
       TII(MF->getSubtarget().getInstrInfo()),
       TRI(MF->getSubtarget().getRegisterInfo()),
       TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
       InsertPos(insertpos) {
-  EmitDebugInstrRefs = UseInstrRefDebugInfo;
+  EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();
 }

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h

@@ -156,8 +156,7 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
   /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
   /// at the given position in the given block.
   InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
-               MachineBasicBlock::iterator insertpos,
-               bool UseInstrRefDebugInfo);
+               MachineBasicBlock::iterator insertpos);
 
 private:
   void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

@@ -778,8 +778,7 @@ void ScheduleDAGLinearize::Schedule() {
 
 MachineBasicBlock*
 ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
-  InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos,
-                       DAG->getUseInstrRefDebugInfo());
+  InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
   DenseMap<SDValue, Register> VRBaseMap;
 
   LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; });

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

@@ -848,8 +848,7 @@ EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
 /// not necessarily refer to returned BB. The emitter may split blocks.
 MachineBasicBlock *ScheduleDAGSDNodes::
 EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
-  InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos,
-                       DAG->getUseInstrRefDebugInfo());
+  InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
   DenseMap<SDValue, Register> VRBaseMap;
   DenseMap<SUnit*, Register> CopyVRBaseMap;
   SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -392,8 +392,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
 
   // Decide what flavour of variable location debug-info will be used, before
   // we change the optimisation level.
-  UseInstrRefDebugInfo = mf.useDebugInstrRef();
-  CurDAG->useInstrRefDebugInfo(UseInstrRefDebugInfo);
+  bool InstrRef = mf.shouldUseDebugInstrRef();
+  mf.setUseDebugInstrRef(InstrRef);
 
   // Reset the target options before resetting the optimization
   // level below.
@@ -546,7 +546,6 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
         LiveInMap.insert(LI);
 
   // Insert DBG_VALUE instructions for function arguments to the entry block.
-  bool InstrRef = MF->useDebugInstrRef();
   for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
     MachineInstr *MI = FuncInfo->ArgDbgValues[e - i - 1];
     assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
@@ -624,7 +623,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
 
   // For debug-info, in instruction referencing mode, we need to perform some
   // post-isel maintenence.
-  if (UseInstrRefDebugInfo)
+  if (MF->useDebugInstrRef())
     MF->finalizeDebugInstrRefs();
 
   // Determine if there are any calls in this machine function.
@@ -1380,8 +1379,6 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
   if (TM.Options.EnableFastISel) {
     LLVM_DEBUG(dbgs() << "Enabling fast-isel\n");
     FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
-    if (FastIS)
-      FastIS->useInstrRefDebugInfo(UseInstrRefDebugInfo);
   }
 
   ReversePostOrderTraversal<const Function*> RPOT(&Fn);

llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir

@@ -32,6 +32,7 @@
 ---
 name:            foo
 tracksRegLiveness: true
+debugInstrRef: true
 debugValueSubstitutions:
   - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 }
 body:             |

llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir

@@ -73,6 +73,7 @@ name:            c
 alignment:       16
 tracksRegLiveness: true
 tracksDebugUserValues: true
+debugInstrRef: true
 frameInfo:
   maxAlignment:    4
 machineFunctionInfo: {}

llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir

@@ -50,6 +50,7 @@
 name:            foo
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$edi' }
 frameInfo:

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir

@@ -86,6 +86,7 @@
 name:            foo
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir

@@ -45,6 +45,7 @@
 name:            foo
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir

@@ -98,6 +98,7 @@
 name:            foo
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir

@@ -99,6 +99,7 @@
 name:            foo
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir

@@ -138,6 +138,7 @@
 name:            _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir

@@ -99,6 +99,7 @@
 name:            _Z3foo10NonTrivial
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 tracksDebugUserValues: true
 liveins:
   - { reg: '$rdi' }

llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir

@@ -178,6 +178,7 @@
 name:            _ZNSt5dequeIPN4llvm4LoopESaIS2_EE13_M_insert_auxESt15_Deque_iteratorIS2_RS2_PS2_EmRKS2_
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi' }
   - { reg: '$rsi' }

llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir

@@ -2,10 +2,12 @@
 #
 # REQUIRES: x86-registered-target
 #
+# CHECK: debugInstrRef: true
 # CHECK: MOV64rr $rdi, debug-instr-number 1
 ---
 name: test
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi', virtual-reg: '' }
 body:  |

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues-transfer-variadic-instr-ref.mir

@@ -155,6 +155,7 @@ name:            _Z3fooii
 alignment:       16
 tracksRegLiveness: true
 tracksDebugUserValues: true
+debugInstrRef: true
 registers:       []
 liveins:
   - { reg: '$edi', virtual-reg: '' }

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir

@@ -37,6 +37,7 @@
 ...
 ---
 name: _Z8bb_to_bb
+debugInstrRef: true
 debugValueSubstitutions:
   - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
 body:  |

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir

@@ -31,6 +31,7 @@
 ...
 ---
 name: _Z8bb_to_bb
+debugInstrRef: true
 debugValueSubstitutions:
   - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
 body:  |

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir

@@ -50,6 +50,7 @@
 ...
 ---
 name: _Z8bb_to_bb
+debugInstrRef: true
 stack:
   - { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4 }
 body:  |

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir

@@ -29,6 +29,7 @@
 ---
 name: test
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi', virtual-reg: '' }
 stack:

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir

@@ -31,6 +31,7 @@
 ---
 name: test
 tracksRegLiveness: true
+debugInstrRef: true
 liveins:
   - { reg: '$rdi', virtual-reg: '' }
 debugValueSubstitutions:

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir

@@ -57,6 +57,7 @@
 name:            _ZNK4llvm5APInt5magicEv
 alignment:       16
 tracksRegLiveness: true
+debugInstrRef: true
 registers:
   - { id: 0, class: gr64 }
   - { id: 1, class: gr32 }