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[LLVM][AArch64] Relax SVE/SME codegen predicates.
Code generation predicates like HasSVE2_or_SME implemented a strict divide between streaming and non-streaming which meant some SME instructions where not available unless a matching SVE feature was enabled. As a specific example, in order to enable multi-register WHILE instructions in non-streaming mode a user must enable "sve2p1" when using "sme2" should be sufficient. This PR seperates the streaming/non-streaming requirement from a features's SVE/SME designation, which in most cases means "+sveX[pY]" and "+sve,+smeVpW" can be used interchangeable when an instruction is available via "+sveX[pY]" or "+smeVpW". NOTE: In some instances this means the compiler will support unsupported configurations, which is fine. NOTE: This PR does not fix all the predicates as I plan to follow up with other PRs to relax the crypto, bitperm and fp8 features.
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‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,11 +58,11 @@ include "AArch64SystemOperands.td"
5858

5959
class AArch64Unsupported { list<Predicate> F; }
6060

61-
let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_SME2p1] in
61+
let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
6262
def SVE2p1Unsupported : AArch64Unsupported;
6363

6464
def SVE2Unsupported : AArch64Unsupported {
65-
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
65+
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
6666
HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4, HasSVEBitPerm,
6767
HasSVEB16B16],
6868
SVE2p1Unsupported.F);
@@ -85,9 +85,9 @@ def SME2p1Unsupported : AArch64Unsupported {
8585
}
8686

8787
def SME2Unsupported : AArch64Unsupported {
88-
let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
88+
let F = !listconcat([HasSME2, HasNonStreamingSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
8989
HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
90-
HasNonStreamingSVE2_or_SSVE_AES],
90+
HasNonStreamingSVE2_or_SSVE_AES, HasSVE2p1_or_StreamingSME2],
9191
SME2p1Unsupported.F);
9292
}
9393

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -249,22 +249,23 @@ def HasSVE_or_SME
249249
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
250250
"sve or sme">;
251251
def HasNonStreamingSVE_or_SME2p2
252-
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
252+
: Predicate<"Subtarget->isSVEAvailable() ||"
253253
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
254254
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
255255
"sve or sme2p2">;
256256
def HasNonStreamingSVE_or_SSVE_FEXPA
257-
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
257+
: Predicate<"Subtarget->isSVEAvailable() ||"
258258
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,
259259
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_FEXPA),
260260
"sve or ssve-fexpa">;
261261

262262
def HasSVE2_or_SME
263-
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
263+
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2() || Subtarget->hasSME())">,
264264
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),
265265
"sve2 or sme">;
266-
def HasSVE2_or_SME2
267-
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
266+
def HasNonStreamingSVE2_or_SME2
267+
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
268+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2())">,
268269
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),
269270
"sve2 or sme2">;
270271
def HasNonStreamingSVE2_or_SSVE_AES
@@ -274,17 +275,22 @@ def HasNonStreamingSVE2_or_SSVE_AES
274275
"sve2 or ssve-aes">;
275276

276277
def HasSVE2p1_or_SME
277-
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
278+
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME())">,
278279
AssemblerPredicateWithAll<(any_of FeatureSME, FeatureSVE2p1),
279280
"sme or sve2p1">;
280281
def HasSVE2p1_or_SME2
281-
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
282+
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2())">,
282283
AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1),
283284
"sme2 or sve2p1">;
284285
def HasSVE2p1_or_SME2p1
285-
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2p1())">,
286+
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2p1())">,
286287
AssemblerPredicateWithAll<(any_of FeatureSME2p1, FeatureSVE2p1),
287288
"sme2p1 or sve2p1">;
289+
def HasSVE2p1_or_StreamingSME2
290+
: Predicate<"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVE2p1()) ||"
291+
"(Subtarget->isStreaming() && Subtarget->hasSME2())">,
292+
AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1),
293+
"sme2 or sve2p1">;
288294

289295
def HasSVE2p2_or_SME2p2
290296
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2())">,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 23 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -4154,18 +4154,29 @@ defm UDOT_ZZZ_HtoS : sve2p1_two_way_dot_vv<"udot", 0b1, int_aarch64_sve_udot_x2
41544154
defm SDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"sdot", 0b0, int_aarch64_sve_sdot_lane_x2>;
41554155
defm UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1, int_aarch64_sve_udot_lane_x2>;
41564156

4157-
defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
4158-
defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext", int_aarch64_sve_pext>;
4159-
defm PEXT_2PCI : sve2p1_pred_as_ctr_to_mask_pair<"pext">;
4160-
defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;
4161-
41624157
defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00, int_aarch64_sve_sqcvtn_x2>;
41634158
defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01, int_aarch64_sve_uqcvtn_x2>;
41644159
defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10, int_aarch64_sve_sqcvtun_x2>;
41654160
defm SQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101, int_aarch64_sve_sqrshrn_x2>;
41664161
defm UQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111, int_aarch64_sve_uqrshrn_x2>;
41674162
defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001, int_aarch64_sve_sqrshrun_x2>;
41684163

4164+
defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>;
4165+
defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>;
4166+
defm WHILELT_2PXX : sve2p1_int_while_rr_pair<"whilelt", 0b010>;
4167+
defm WHILELE_2PXX : sve2p1_int_while_rr_pair<"whilele", 0b011>;
4168+
defm WHILEHS_2PXX : sve2p1_int_while_rr_pair<"whilehs", 0b100>;
4169+
defm WHILEHI_2PXX : sve2p1_int_while_rr_pair<"whilehi", 0b101>;
4170+
defm WHILELO_2PXX : sve2p1_int_while_rr_pair<"whilelo", 0b110>;
4171+
defm WHILELS_2PXX : sve2p1_int_while_rr_pair<"whilels", 0b111>;
4172+
} // End HasSVE2p1_or_SME2
4173+
4174+
let Predicates = [HasSVE2p1_or_StreamingSME2] in {
4175+
defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
4176+
defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext", int_aarch64_sve_pext>;
4177+
defm PEXT_2PCI : sve2p1_pred_as_ctr_to_mask_pair<"pext">;
4178+
defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;
4179+
41694180
// Load to two registers
41704181
defm LD1B_2Z : sve2p1_mem_cld_ss_2z<"ld1b", 0b00, 0b0, ZZ_b_mul_r, GPR64shifted8, ZZ_b_strided_and_contiguous>;
41714182
defm LD1H_2Z : sve2p1_mem_cld_ss_2z<"ld1h", 0b01, 0b0, ZZ_h_mul_r, GPR64shifted16, ZZ_h_strided_and_contiguous>;
@@ -4289,14 +4300,6 @@ defm : store_pn_x4<nxv8bf16, int_aarch64_sve_stnt1_pn_x4, STNT1H_4Z_IMM>;
42894300
defm : store_pn_x4<nxv4f32, int_aarch64_sve_stnt1_pn_x4, STNT1W_4Z_IMM>;
42904301
defm : store_pn_x4<nxv2f64, int_aarch64_sve_stnt1_pn_x4, STNT1D_4Z_IMM>;
42914302

4292-
defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>;
4293-
defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>;
4294-
defm WHILELT_2PXX : sve2p1_int_while_rr_pair<"whilelt", 0b010>;
4295-
defm WHILELE_2PXX : sve2p1_int_while_rr_pair<"whilele", 0b011>;
4296-
defm WHILEHS_2PXX : sve2p1_int_while_rr_pair<"whilehs", 0b100>;
4297-
defm WHILEHI_2PXX : sve2p1_int_while_rr_pair<"whilehi", 0b101>;
4298-
defm WHILELO_2PXX : sve2p1_int_while_rr_pair<"whilelo", 0b110>;
4299-
defm WHILELS_2PXX : sve2p1_int_while_rr_pair<"whilels", 0b111>;
43004303
defm WHILEGE_CXX : sve2p1_int_while_rr_pn<"whilege", 0b000>;
43014304
defm WHILEGT_CXX : sve2p1_int_while_rr_pn<"whilegt", 0b001>;
43024305
defm WHILELT_CXX : sve2p1_int_while_rr_pn<"whilelt", 0b010>;
@@ -4305,7 +4308,7 @@ defm WHILEHS_CXX : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
43054308
defm WHILEHI_CXX : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
43064309
defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
43074310
defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
4308-
} // End HasSVE2p1_or_SME2
4311+
} // End HasSVE2p1_or_StreamingSME2
43094312

43104313
let Predicates = [HasSVE_or_SME] in {
43114314

@@ -4510,7 +4513,7 @@ let Predicates = [HasNonStreamingSVE2p2_or_SME2p2] in {
45104513
//===----------------------------------------------------------------------===//
45114514
// SVE2 FP8 instructions
45124515
//===----------------------------------------------------------------------===//
4513-
let Predicates = [HasSVE2_or_SME2, HasFP8] in {
4516+
let Predicates = [HasNonStreamingSVE2_or_SME2, HasFP8] in {
45144517
// FP8 upconvert
45154518
defm F1CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b00, "f1cvt", nxv8f16, int_aarch64_sve_fp8_cvt1>;
45164519
defm F2CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b01, "f2cvt", nxv8f16, int_aarch64_sve_fp8_cvt2>;
@@ -4527,15 +4530,15 @@ defm FCVTNB_Z2Z_StoB : sve2_fp8_down_cvt_single<0b01, "fcvtnb", ZZ_s_mul_r, nxv4
45274530
defm BFCVTN_Z2Z_HtoB : sve2_fp8_down_cvt_single<0b10, "bfcvtn", ZZ_h_mul_r, nxv8bf16, int_aarch64_sve_fp8_cvtn>;
45284531

45294532
defm FCVTNT_Z2Z_StoB : sve2_fp8_down_cvt_single_top<0b11, "fcvtnt", ZZ_s_mul_r, nxv4f32, int_aarch64_sve_fp8_cvtnt>;
4530-
} // End HasSVE2_or_SME2, HasFP8
4533+
} // End HasNonStreamingSVE2_or_SME2, HasFP8
45314534

4532-
let Predicates = [HasSVE2_or_SME2, HasFAMINMAX] in {
4535+
let Predicates = [HasNonStreamingSVE2_or_SME2, HasFAMINMAX] in {
45334536
defm FAMIN_ZPmZ : sve_fp_2op_p_zds<0b1111, "famin", "FAMIN_ZPZZ", int_aarch64_sve_famin, DestructiveBinaryComm>;
45344537
defm FAMAX_ZPmZ : sve_fp_2op_p_zds<0b1110, "famax", "FAMAX_ZPZZ", int_aarch64_sve_famax, DestructiveBinaryComm>;
45354538

45364539
defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd<AArch64famax_p>;
45374540
defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd<AArch64famin_p>;
4538-
} // End HasSVE2_or_SME2, HasFAMINMAX
4541+
} // End HasNonStreamingSVE2_or_SME2, HasFAMINMAX
45394542

45404543
let Predicates = [HasSSVE_FP8FMA] in {
45414544
// FP8 Widening Multiply-Add Long - Indexed Group
@@ -4579,14 +4582,14 @@ defm FDOT_ZZZI_BtoS : sve2_fp8_dot_indexed_s<"fdot", int_aarch64_sve_fp8_fdot_la
45794582
defm FDOT_ZZZ_BtoS : sve_fp8_dot<0b1, ZPR32, "fdot", nxv4f32, int_aarch64_sve_fp8_fdot>;
45804583
}
45814584

4582-
let Predicates = [HasSVE2_or_SME2, HasLUT] in {
4585+
let Predicates = [HasNonStreamingSVE2_or_SME2, HasLUT] in {
45834586
// LUTI2
45844587
defm LUTI2_ZZZI : sve2_luti2_vector_index<"luti2">;
45854588
// LUTI4
45864589
defm LUTI4_ZZZI : sve2_luti4_vector_index<"luti4">;
45874590
// LUTI4 (two contiguous registers)
45884591
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
4589-
} // End HasSVE2_or_SME2, HasLUT
4592+
} // End HasNonStreamingSVE2_or_SME2, HasLUT
45904593

45914594
//===----------------------------------------------------------------------===//
45924595
// Checked Pointer Arithmetic (FEAT_CPA)

‎llvm/test/CodeGen/AArch64/fp8-sve-cvt-cvtlt.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s
3+
; RUN: llc -mattr=+sve,+sme2,+fp8 < %s | FileCheck %s
34
; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s
45

56
target triple = "aarch64-linux"

‎llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s
3+
; RUN: llc -mattr=+sve,+sme2,+fp8 < %s | FileCheck %s
34
; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s
45

56
target triple = "aarch64-linux"

‎llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3-
; RUN: llc -mtriple=aarch64-linux-gnu -force-streaming -mattr=+ssve-fexpa < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+ssve-fexpa -force-streaming < %s | FileCheck %s
44

55
define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
66
; CHECK-LABEL: fexpa_h:
@@ -27,4 +27,4 @@ define <vscale x 2 x double> @fexpa_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64>
2727
; CHECK-NEXT: ret
2828
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %a)
2929
ret <vscale x 2 x double> %out
30-
}
30+
}

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
45

56
; ADDHNB

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
45

56
;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-complex-dot.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
45

56
;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
45

56
;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes < %s | FileCheck %s
33
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2,+sve-aes < %s | FileCheck %s
4+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+ssve-aes < %s | FileCheck %s
5+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+ssve-aes -force-streaming < %s | FileCheck %s
46

57
;
68
; AESD

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-faminmax.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mattr=+sve,+sme2 < %s | FileCheck %s
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; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
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target triple = "aarch64-linux"

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sve2,+lut,+bf16 | FileCheck %s
2+
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sve2,+lut | FileCheck %s
3+
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sve,+sme2,+lut | FileCheck %s
4+
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sme2,+lut --force-streaming | FileCheck %s
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define <vscale x 16 x i8> @test_luti2_lane_i8(<vscale x 16 x i8> %table, <vscale x 16 x i8> %indices){
57
; CHECK-LABEL: test_luti2_lane_i8:

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-non-widening-pairwise-arith.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic-128.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2,+sve-aes < %s | FileCheck %s
4+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+ssve-aes < %s | FileCheck %s
5+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+ssve-aes -force-streaming < %s | FileCheck %s
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;
58
; PMULLB

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-psel.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,sme -verify-machineinstrs < %s | FileCheck %s
24
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 16 x i1> @psel_b(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx) {

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-revd.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s
24
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 16 x i8> @test_revd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-complex-arith.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-dsp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
34
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;

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