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[LoongArch] Add codegen support for icmp/fcmp with lsx/lasx fetaures (#74700)
Mark ISD::SETCC node as legal, and add handling for the vector types condition codes.
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‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -247,6 +247,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
247247
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
248248
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
249249

250+
setOperationAction(ISD::SETCC, VT, Legal);
250251
setOperationAction(ISD::VSELECT, VT, Legal);
251252
}
252253
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) {
@@ -260,11 +261,17 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
260261
setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal);
261262
setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal);
262263
setOperationAction({ISD::MULHS, ISD::MULHU}, VT, Legal);
264+
setCondCodeAction(
265+
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
266+
Expand);
263267
}
264268
for (MVT VT : {MVT::v4f32, MVT::v2f64}) {
265269
setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
266270
setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);
267271
setOperationAction(ISD::FMA, VT, Legal);
272+
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
273+
ISD::SETUGE, ISD::SETUGT},
274+
VT, Expand);
268275
}
269276
}
270277

@@ -280,6 +287,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
280287
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
281288
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
282289

290+
setOperationAction(ISD::SETCC, VT, Legal);
283291
setOperationAction(ISD::VSELECT, VT, Legal);
284292
}
285293
for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) {
@@ -293,11 +301,17 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
293301
setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal);
294302
setOperationAction({ISD::CTPOP, ISD::CTLZ}, VT, Legal);
295303
setOperationAction({ISD::MULHS, ISD::MULHU}, VT, Legal);
304+
setCondCodeAction(
305+
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
306+
Expand);
296307
}
297308
for (MVT VT : {MVT::v8f32, MVT::v4f64}) {
298309
setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
299310
setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);
300311
setOperationAction(ISD::FMA, VT, Legal);
312+
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
313+
ISD::SETUGE, ISD::SETUGT},
314+
VT, Expand);
301315
}
302316
}
303317

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1184,6 +1184,65 @@ multiclass PatShiftXrUimm<SDPatternOperator OpNode, string Inst> {
11841184
(!cast<LAInst>(Inst#"_D") LASX256:$xj, uimm6:$imm)>;
11851185
}
11861186

1187+
multiclass PatCCXrSimm5<CondCode CC, string Inst> {
1188+
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj),
1189+
(v32i8 (SplatPat_simm5 simm5:$imm)), CC)),
1190+
(!cast<LAInst>(Inst#"_B") LASX256:$xj, simm5:$imm)>;
1191+
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj),
1192+
(v16i16 (SplatPat_simm5 simm5:$imm)), CC)),
1193+
(!cast<LAInst>(Inst#"_H") LASX256:$xj, simm5:$imm)>;
1194+
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj),
1195+
(v8i32 (SplatPat_simm5 simm5:$imm)), CC)),
1196+
(!cast<LAInst>(Inst#"_W") LASX256:$xj, simm5:$imm)>;
1197+
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj),
1198+
(v4i64 (SplatPat_simm5 simm5:$imm)), CC)),
1199+
(!cast<LAInst>(Inst#"_D") LASX256:$xj, simm5:$imm)>;
1200+
}
1201+
1202+
multiclass PatCCXrUimm5<CondCode CC, string Inst> {
1203+
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj),
1204+
(v32i8 (SplatPat_uimm5 uimm5:$imm)), CC)),
1205+
(!cast<LAInst>(Inst#"_BU") LASX256:$xj, uimm5:$imm)>;
1206+
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj),
1207+
(v16i16 (SplatPat_uimm5 uimm5:$imm)), CC)),
1208+
(!cast<LAInst>(Inst#"_HU") LASX256:$xj, uimm5:$imm)>;
1209+
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj),
1210+
(v8i32 (SplatPat_uimm5 uimm5:$imm)), CC)),
1211+
(!cast<LAInst>(Inst#"_WU") LASX256:$xj, uimm5:$imm)>;
1212+
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj),
1213+
(v4i64 (SplatPat_uimm5 uimm5:$imm)), CC)),
1214+
(!cast<LAInst>(Inst#"_DU") LASX256:$xj, uimm5:$imm)>;
1215+
}
1216+
1217+
multiclass PatCCXrXr<CondCode CC, string Inst> {
1218+
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj), (v32i8 LASX256:$xk), CC)),
1219+
(!cast<LAInst>(Inst#"_B") LASX256:$xj, LASX256:$xk)>;
1220+
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj), (v16i16 LASX256:$xk), CC)),
1221+
(!cast<LAInst>(Inst#"_H") LASX256:$xj, LASX256:$xk)>;
1222+
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj), (v8i32 LASX256:$xk), CC)),
1223+
(!cast<LAInst>(Inst#"_W") LASX256:$xj, LASX256:$xk)>;
1224+
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj), (v4i64 LASX256:$xk), CC)),
1225+
(!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
1226+
}
1227+
1228+
multiclass PatCCXrXrU<CondCode CC, string Inst> {
1229+
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj), (v32i8 LASX256:$xk), CC)),
1230+
(!cast<LAInst>(Inst#"_BU") LASX256:$xj, LASX256:$xk)>;
1231+
def : Pat<(v16i16 (setcc (v16i16 LASX256:$xj), (v16i16 LASX256:$xk), CC)),
1232+
(!cast<LAInst>(Inst#"_HU") LASX256:$xj, LASX256:$xk)>;
1233+
def : Pat<(v8i32 (setcc (v8i32 LASX256:$xj), (v8i32 LASX256:$xk), CC)),
1234+
(!cast<LAInst>(Inst#"_WU") LASX256:$xj, LASX256:$xk)>;
1235+
def : Pat<(v4i64 (setcc (v4i64 LASX256:$xj), (v4i64 LASX256:$xk), CC)),
1236+
(!cast<LAInst>(Inst#"_DU") LASX256:$xj, LASX256:$xk)>;
1237+
}
1238+
1239+
multiclass PatCCXrXrF<CondCode CC, string Inst> {
1240+
def : Pat<(v8i32 (setcc (v8f32 LASX256:$xj), (v8f32 LASX256:$xk), CC)),
1241+
(!cast<LAInst>(Inst#"_S") LASX256:$xj, LASX256:$xk)>;
1242+
def : Pat<(v4i64 (setcc (v4f64 LASX256:$xj), (v4f64 LASX256:$xk), CC)),
1243+
(!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
1244+
}
1245+
11871246
let Predicates = [HasExtLASX] in {
11881247

11891248
// XVADD_{B/H/W/D}
@@ -1389,6 +1448,42 @@ def : Pat<(fma v8f32:$xj, v8f32:$xk, v8f32:$xa),
13891448
def : Pat<(fma v4f64:$xj, v4f64:$xk, v4f64:$xa),
13901449
(XVFMADD_D v4f64:$xj, v4f64:$xk, v4f64:$xa)>;
13911450

1451+
// XVSEQ[I]_{B/H/W/D}
1452+
defm : PatCCXrSimm5<SETEQ, "XVSEQI">;
1453+
defm : PatCCXrXr<SETEQ, "XVSEQ">;
1454+
1455+
// XVSLE[I]_{B/H/W/D}[U]
1456+
defm : PatCCXrSimm5<SETLE, "XVSLEI">;
1457+
defm : PatCCXrUimm5<SETULE, "XVSLEI">;
1458+
defm : PatCCXrXr<SETLE, "XVSLE">;
1459+
defm : PatCCXrXrU<SETULE, "XVSLE">;
1460+
1461+
// XVSLT[I]_{B/H/W/D}[U]
1462+
defm : PatCCXrSimm5<SETLT, "XVSLTI">;
1463+
defm : PatCCXrUimm5<SETULT, "XVSLTI">;
1464+
defm : PatCCXrXr<SETLT, "XVSLT">;
1465+
defm : PatCCXrXrU<SETULT, "XVSLT">;
1466+
1467+
// XVFCMP.cond.{S/D}
1468+
defm : PatCCXrXrF<SETEQ, "XVFCMP_CEQ">;
1469+
defm : PatCCXrXrF<SETOEQ, "XVFCMP_CEQ">;
1470+
defm : PatCCXrXrF<SETUEQ, "XVFCMP_CUEQ">;
1471+
1472+
defm : PatCCXrXrF<SETLE, "XVFCMP_CLE">;
1473+
defm : PatCCXrXrF<SETOLE, "XVFCMP_CLE">;
1474+
defm : PatCCXrXrF<SETULE, "XVFCMP_CULE">;
1475+
1476+
defm : PatCCXrXrF<SETLT, "XVFCMP_CLT">;
1477+
defm : PatCCXrXrF<SETOLT, "XVFCMP_CLT">;
1478+
defm : PatCCXrXrF<SETULT, "XVFCMP_CULT">;
1479+
1480+
defm : PatCCXrXrF<SETNE, "XVFCMP_CNE">;
1481+
defm : PatCCXrXrF<SETONE, "XVFCMP_CNE">;
1482+
defm : PatCCXrXrF<SETUNE, "XVFCMP_CUNE">;
1483+
1484+
defm : PatCCXrXrF<SETO, "XVFCMP_COR">;
1485+
defm : PatCCXrXrF<SETUO, "XVFCMP_CUN">;
1486+
13921487
// PseudoXVINSGR2VR_{B/H}
13931488
def : Pat<(vector_insert v32i8:$xd, GRLenVT:$rj, uimm5:$imm),
13941489
(PseudoXVINSGR2VR_B v32i8:$xd, GRLenVT:$rj, uimm5:$imm)>;

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1261,6 +1261,65 @@ multiclass PatShiftVrUimm<SDPatternOperator OpNode, string Inst> {
12611261
(!cast<LAInst>(Inst#"_D") LSX128:$vj, uimm6:$imm)>;
12621262
}
12631263

1264+
multiclass PatCCVrSimm5<CondCode CC, string Inst> {
1265+
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj),
1266+
(v16i8 (SplatPat_simm5 simm5:$imm)), CC)),
1267+
(!cast<LAInst>(Inst#"_B") LSX128:$vj, simm5:$imm)>;
1268+
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj),
1269+
(v8i16 (SplatPat_simm5 simm5:$imm)), CC)),
1270+
(!cast<LAInst>(Inst#"_H") LSX128:$vj, simm5:$imm)>;
1271+
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj),
1272+
(v4i32 (SplatPat_simm5 simm5:$imm)), CC)),
1273+
(!cast<LAInst>(Inst#"_W") LSX128:$vj, simm5:$imm)>;
1274+
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj),
1275+
(v2i64 (SplatPat_simm5 simm5:$imm)), CC)),
1276+
(!cast<LAInst>(Inst#"_D") LSX128:$vj, simm5:$imm)>;
1277+
}
1278+
1279+
multiclass PatCCVrUimm5<CondCode CC, string Inst> {
1280+
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj),
1281+
(v16i8 (SplatPat_uimm5 uimm5:$imm)), CC)),
1282+
(!cast<LAInst>(Inst#"_BU") LSX128:$vj, uimm5:$imm)>;
1283+
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj),
1284+
(v8i16 (SplatPat_uimm5 uimm5:$imm)), CC)),
1285+
(!cast<LAInst>(Inst#"_HU") LSX128:$vj, uimm5:$imm)>;
1286+
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj),
1287+
(v4i32 (SplatPat_uimm5 uimm5:$imm)), CC)),
1288+
(!cast<LAInst>(Inst#"_WU") LSX128:$vj, uimm5:$imm)>;
1289+
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj),
1290+
(v2i64 (SplatPat_uimm5 uimm5:$imm)), CC)),
1291+
(!cast<LAInst>(Inst#"_DU") LSX128:$vj, uimm5:$imm)>;
1292+
}
1293+
1294+
multiclass PatCCVrVr<CondCode CC, string Inst> {
1295+
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)),
1296+
(!cast<LAInst>(Inst#"_B") LSX128:$vj, LSX128:$vk)>;
1297+
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)),
1298+
(!cast<LAInst>(Inst#"_H") LSX128:$vj, LSX128:$vk)>;
1299+
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)),
1300+
(!cast<LAInst>(Inst#"_W") LSX128:$vj, LSX128:$vk)>;
1301+
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)),
1302+
(!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;
1303+
}
1304+
1305+
multiclass PatCCVrVrU<CondCode CC, string Inst> {
1306+
def : Pat<(v16i8 (setcc (v16i8 LSX128:$vj), (v16i8 LSX128:$vk), CC)),
1307+
(!cast<LAInst>(Inst#"_BU") LSX128:$vj, LSX128:$vk)>;
1308+
def : Pat<(v8i16 (setcc (v8i16 LSX128:$vj), (v8i16 LSX128:$vk), CC)),
1309+
(!cast<LAInst>(Inst#"_HU") LSX128:$vj, LSX128:$vk)>;
1310+
def : Pat<(v4i32 (setcc (v4i32 LSX128:$vj), (v4i32 LSX128:$vk), CC)),
1311+
(!cast<LAInst>(Inst#"_WU") LSX128:$vj, LSX128:$vk)>;
1312+
def : Pat<(v2i64 (setcc (v2i64 LSX128:$vj), (v2i64 LSX128:$vk), CC)),
1313+
(!cast<LAInst>(Inst#"_DU") LSX128:$vj, LSX128:$vk)>;
1314+
}
1315+
1316+
multiclass PatCCVrVrF<CondCode CC, string Inst> {
1317+
def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)),
1318+
(!cast<LAInst>(Inst#"_S") LSX128:$vj, LSX128:$vk)>;
1319+
def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)),
1320+
(!cast<LAInst>(Inst#"_D") LSX128:$vj, LSX128:$vk)>;
1321+
}
1322+
12641323
let Predicates = [HasExtLSX] in {
12651324

12661325
// VADD_{B/H/W/D}
@@ -1466,6 +1525,42 @@ def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va),
14661525
def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va),
14671526
(VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
14681527

1528+
// VSEQ[I]_{B/H/W/D}
1529+
defm : PatCCVrSimm5<SETEQ, "VSEQI">;
1530+
defm : PatCCVrVr<SETEQ, "VSEQ">;
1531+
1532+
// VSLE[I]_{B/H/W/D}[U]
1533+
defm : PatCCVrSimm5<SETLE, "VSLEI">;
1534+
defm : PatCCVrUimm5<SETULE, "VSLEI">;
1535+
defm : PatCCVrVr<SETLE, "VSLE">;
1536+
defm : PatCCVrVrU<SETULE, "VSLE">;
1537+
1538+
// VSLT[I]_{B/H/W/D}[U]
1539+
defm : PatCCVrSimm5<SETLT, "VSLTI">;
1540+
defm : PatCCVrUimm5<SETULT, "VSLTI">;
1541+
defm : PatCCVrVr<SETLT, "VSLT">;
1542+
defm : PatCCVrVrU<SETULT, "VSLT">;
1543+
1544+
// VFCMP.cond.{S/D}
1545+
defm : PatCCVrVrF<SETEQ, "VFCMP_CEQ">;
1546+
defm : PatCCVrVrF<SETOEQ, "VFCMP_CEQ">;
1547+
defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">;
1548+
1549+
defm : PatCCVrVrF<SETLE, "VFCMP_CLE">;
1550+
defm : PatCCVrVrF<SETOLE, "VFCMP_CLE">;
1551+
defm : PatCCVrVrF<SETULE, "VFCMP_CULE">;
1552+
1553+
defm : PatCCVrVrF<SETLT, "VFCMP_CLT">;
1554+
defm : PatCCVrVrF<SETOLT, "VFCMP_CLT">;
1555+
defm : PatCCVrVrF<SETULT, "VFCMP_CULT">;
1556+
1557+
defm : PatCCVrVrF<SETNE, "VFCMP_CNE">;
1558+
defm : PatCCVrVrF<SETONE, "VFCMP_CNE">;
1559+
defm : PatCCVrVrF<SETUNE, "VFCMP_CUNE">;
1560+
1561+
defm : PatCCVrVrF<SETO, "VFCMP_COR">;
1562+
defm : PatCCVrVrF<SETUO, "VFCMP_CUN">;
1563+
14691564
// VINSGR2VR_{B/H/W/D}
14701565
def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm),
14711566
(VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>;

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