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fix conditions and add tc to utilitze new supported registers
1 parent c1a696b commit 9ff95f6

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9 files changed

+167
-30
lines changed

9 files changed

+167
-30
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17322,8 +17322,9 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
1732217322

1732317323
Register PPCTargetLowering::getRegisterByName(const char *RegName, LLT VT,
1732417324
const MachineFunction &MF) const {
17325+
bool IsPPC64 = Subtarget.isPPC64();
1732517326

17326-
bool Is64Bit = Subtarget.isPPC64() && VT == LLT::scalar(64);
17327+
bool Is64Bit = IsPPC64 && VT == LLT::scalar(64);
1732717328
if (!Is64Bit && VT != LLT::scalar(32))
1732817329
report_fatal_error("Invalid register global variable type");
1732917330

@@ -17332,6 +17333,12 @@ Register PPCTargetLowering::getRegisterByName(const char *RegName, LLT VT,
1733217333
report_fatal_error(
1733317334
Twine("Invalid global name register \"" + StringRef(RegName) + "\"."));
1733417335

17336+
// FIXME: These registers are not flagged as reserved and we can generate
17337+
// code for `-O0` but not for `-O2`. Need followup investigation as to why.
17338+
if ((IsPPC64 && Reg == PPC::R2) || Reg == PPC::R0)
17339+
report_fatal_error(Twine("Trying to reserve an invalid register \"" +
17340+
StringRef(RegName) + "\"."));
17341+
1733517342
// Convert GPR to GP8R register for 64bit.
1733617343
if (Is64Bit && StringRef(RegName).starts_with_insensitive("r"))
1733717344
Reg = Reg.id() - PPC::R0 + PPC::X0;

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
11
; RUN: not --crash llc -O0 < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
2-
; RUN: not --crash llc -O0 < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
32
; RUN: not --crash llc -O0 < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
43

54
define i32 @get_reg() nounwind {
65
entry:
7-
; CHECK: Trying to obtain non-reservable register "r0".
6+
; CHECK: Trying to reserve an invalid register "r0".
87
%reg = call i32 @llvm.read_register.i32(metadata !0)
98
ret i32 %reg
109
}

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,10 @@
1-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
1+
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
22

33
define i64 @get_reg() nounwind {
4+
; CHECK: Trying to obtain a reserved register "r1".
45
entry:
56
%reg = call i64 @llvm.read_register.i64(metadata !0)
67
ret i64 %reg
7-
8-
; CHECK-LABEL: get_reg
9-
; CHECK: mr 3, 1
108
}
119

1210
declare i64 @llvm.read_register.i64(metadata) nounwind

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r1.ll

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,11 @@
1-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
2-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
1+
; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
2+
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
33

44
define i32 @get_reg() nounwind {
5+
; CHECK: Trying to obtain a reserved register "r1".
56
entry:
67
%reg = call i32 @llvm.read_register.i32(metadata !0)
78
ret i32 %reg
8-
9-
; CHECK-LABEL: @get_reg
10-
; CHECK: mr 3, 1
11-
129
}
1310

1411
declare i32 @llvm.read_register.i32(metadata) nounwind

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,10 @@
1-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
1+
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
22

33
define i64 @get_reg() nounwind {
4+
; CHECK: Trying to obtain a reserved register "r13".
45
entry:
56
%reg = call i64 @llvm.read_register.i64(metadata !0)
67
ret i64 %reg
7-
8-
; CHECK-LABEL: @get_reg
9-
; CHECK: mr 3, 13
10-
118
}
129

1310
declare i64 @llvm.read_register.i64(metadata) nounwind

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r13.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,11 @@
1-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
2-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
1+
; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
2+
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
33

44
define i32 @get_reg() nounwind {
5+
; CHECK: Trying to obtain a reserved register "r13".
56
entry:
67
%reg = call i32 @llvm.read_register.i32(metadata !0)
78
ret i32 %reg
8-
9-
; CHECK-LABEL: @get_reg
10-
; CHECK: mr 3, 13
119
}
1210

1311
declare i32 @llvm.read_register.i32(metadata) nounwind

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,8 @@
11
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
2-
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
32

43
define i64 @get_reg() nounwind {
54
entry:
6-
; CHECK: Trying to obtain non-reservable register "r2".
5+
; CHECK: Trying to reserve an invalid register "r2".
76
%reg = call i64 @llvm.read_register.i64(metadata !0)
87
ret i64 %reg
98
}

‎llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,12 @@
1-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
1+
; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
22
; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32
33

44
define i32 @get_reg() nounwind {
55
entry:
6-
; CHECK-NOTPPC32: Trying to obtain non-reservable register "r2".
6+
; CHECK-NOTPPC32: Trying to reserve an invalid register "r2".
7+
; CHECK: Trying to obtain a reserved register "r2".
78
%reg = call i32 @llvm.read_register.i32(metadata !0)
89
ret i32 %reg
9-
10-
; CHECK-LABEL: @get_reg
11-
; CHECK: mr 3, 2
1210
}
1311

1412
declare i32 @llvm.read_register.i32(metadata) nounwind

‎llvm/test/CodeGen/PowerPC/named-reg-alloc.ll

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,144 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -O0 -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
3+
; RUN: llc -O0 -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK64
4+
5+
@mVal = dso_local global i32 15, align 4
6+
@myGVal = dso_local global i32 0, align 4
7+
8+
define dso_local void @testSetIntReg(i32 noundef signext %xx) {
9+
; CHECK-LABEL: testSetIntReg:
10+
; CHECK: # %bb.0: # %entry
11+
; CHECK-NEXT: mr 5, 3
12+
; CHECK-NEXT: blr
13+
;
14+
; CHECK64-LABEL: testSetIntReg:
15+
; CHECK64: # %bb.0: # %entry
16+
; CHECK64-NEXT: mr 5, 3
17+
; CHECK64-NEXT: blr
18+
entry:
19+
tail call void @llvm.write_register.i32(metadata !0, i32 %xx)
20+
ret void
21+
}
22+
23+
declare void @llvm.write_register.i32(metadata, i32)
24+
25+
define dso_local signext range(i32 0, 2) i32 @testCmpReg() {
26+
; CHECK-LABEL: testCmpReg:
27+
; CHECK: # %bb.0: # %entry
28+
; CHECK-NEXT: lis 3, mVal@ha
29+
; CHECK-NEXT: lwz 3, mVal@l(3)
30+
; CHECK-NEXT: xori 3, 3, 15
31+
; CHECK-NEXT: cntlzw 3, 3
32+
; CHECK-NEXT: srwi 3, 3, 5
33+
; CHECK-NEXT: blr
34+
;
35+
; CHECK64-LABEL: testCmpReg:
36+
; CHECK64: # %bb.0: # %entry
37+
; CHECK64-NEXT: addis 3, 2, mVal@toc@ha
38+
; CHECK64-NEXT: addi 3, 3, mVal@toc@l
39+
; CHECK64-NEXT: lwz 3, 0(3)
40+
; CHECK64-NEXT: xori 3, 3, 15
41+
; CHECK64-NEXT: cntlzw 3, 3
42+
; CHECK64-NEXT: srwi 3, 3, 5
43+
; CHECK64-NEXT: extsw 3, 3
44+
; CHECK64-NEXT: blr
45+
entry:
46+
tail call void @llvm.write_register.i32(metadata !0, i32 15)
47+
%0 = load i32, ptr @mVal, align 4
48+
%1 = tail call i32 @llvm.read_register.i32(metadata !0)
49+
%cmp = icmp eq i32 %0, %1
50+
%conv = zext i1 %cmp to i32
51+
ret i32 %conv
52+
}
53+
54+
declare i32 @llvm.read_register.i32(metadata)
55+
56+
define dso_local void @testSetIntReg2(i32 noundef signext %xx) {
57+
; CHECK-LABEL: testSetIntReg2:
58+
; CHECK: # %bb.0: # %entry
59+
; CHECK-NEXT: stwu 1, -48(1)
60+
; CHECK-NEXT: .cfi_def_cfa_offset 48
61+
; CHECK-NEXT: .cfi_offset r23, -36
62+
; CHECK-NEXT: stw 23, 12(1) # 4-byte Folded Spill
63+
; CHECK-NEXT: mr 23, 3
64+
; CHECK-NEXT: lwz 23, 12(1) # 4-byte Folded Reload
65+
; CHECK-NEXT: addi 1, 1, 48
66+
; CHECK-NEXT: blr
67+
;
68+
; CHECK64-LABEL: testSetIntReg2:
69+
; CHECK64: # %bb.0: # %entry
70+
; CHECK64-NEXT: std 23, -72(1) # 8-byte Folded Spill
71+
; CHECK64-NEXT: mr 23, 3
72+
; CHECK64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
73+
; CHECK64-NEXT: blr
74+
entry:
75+
tail call void @llvm.write_register.i32(metadata !1, i32 %xx)
76+
ret void
77+
}
78+
79+
define dso_local signext i32 @testReturnReg() {
80+
; CHECK-LABEL: testReturnReg:
81+
; CHECK: # %bb.0: # %entry
82+
; CHECK-NEXT: stwu 1, -48(1)
83+
; CHECK-NEXT: .cfi_def_cfa_offset 48
84+
; CHECK-NEXT: .cfi_offset r23, -36
85+
; CHECK-NEXT: stw 23, 12(1) # 4-byte Folded Spill
86+
; CHECK-NEXT: li 23, 125
87+
; CHECK-NEXT: mr 3, 23
88+
; CHECK-NEXT: lwz 23, 12(1) # 4-byte Folded Reload
89+
; CHECK-NEXT: addi 1, 1, 48
90+
; CHECK-NEXT: blr
91+
;
92+
; CHECK64-LABEL: testReturnReg:
93+
; CHECK64: # %bb.0: # %entry
94+
; CHECK64-NEXT: std 23, -72(1) # 8-byte Folded Spill
95+
; CHECK64-NEXT: li 23, 125
96+
; CHECK64-NEXT: extsw 3, 23
97+
; CHECK64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
98+
; CHECK64-NEXT: blr
99+
entry:
100+
tail call void @llvm.write_register.i32(metadata !1, i32 125)
101+
%0 = tail call i32 @llvm.read_register.i32(metadata !1)
102+
ret i32 %0
103+
}
104+
105+
define dso_local void @testViaASM(i32 noundef signext %xx) {
106+
; CHECK-LABEL: testViaASM:
107+
; CHECK: # %bb.0: # %entry
108+
; CHECK-NEXT: stwu 1, -64(1)
109+
; CHECK-NEXT: .cfi_def_cfa_offset 64
110+
; CHECK-NEXT: .cfi_offset r20, -48
111+
; CHECK-NEXT: stw 20, 16(1) # 4-byte Folded Spill
112+
; CHECK-NEXT: mr 20, 3
113+
; CHECK-NEXT: #APP
114+
; CHECK-NEXT: addi 3, 1, 1
115+
; CHECK-NEXT: #NO_APP
116+
; CHECK-NEXT: lis 4, myGVal@ha
117+
; CHECK-NEXT: stw 3, myGVal@l(4)
118+
; CHECK-NEXT: lwz 20, 16(1) # 4-byte Folded Reload
119+
; CHECK-NEXT: addi 1, 1, 64
120+
; CHECK-NEXT: blr
121+
;
122+
; CHECK64-LABEL: testViaASM:
123+
; CHECK64: # %bb.0: # %entry
124+
; CHECK64-NEXT: std 20, -96(1) # 8-byte Folded Spill
125+
; CHECK64-NEXT: mr 20, 3
126+
; CHECK64-NEXT: #APP
127+
; CHECK64-NEXT: addi 3, 1, 1
128+
; CHECK64-NEXT: #NO_APP
129+
; CHECK64-NEXT: addis 4, 2, myGVal@toc@ha
130+
; CHECK64-NEXT: addi 4, 4, myGVal@toc@l
131+
; CHECK64-NEXT: stw 3, 0(4)
132+
; CHECK64-NEXT: ld 20, -96(1) # 8-byte Folded Reload
133+
; CHECK64-NEXT: blr
134+
entry:
135+
tail call void @llvm.write_register.i32(metadata !2, i32 %xx)
136+
%0 = tail call i32 @llvm.read_register.i32(metadata !2)
137+
%1 = tail call i32 asm "addi $0, $2, $2", "=r,{r20},K"(i32 %0, i32 1)
138+
store i32 %1, ptr @myGVal, align 4
139+
ret void
140+
}
141+
142+
!0 = !{!"r5"}
143+
!1 = !{!"r23"}
144+
!2 = !{!"r20"}

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