Skip to content

Commit a01392c

Browse files
vpykhtinvpykhtin
authored
[AMDGPU] Set debug info on CFG annotation instructions. (#73958)
This fixes incorrect source location in ASAN diagnostics for #72247.
1 parent f65e3af commit a01392c

File tree

2 files changed

+43
-32
lines changed

2 files changed

+43
-32
lines changed

‎llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp

Lines changed: 25 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "llvm/IR/BasicBlock.h"
2020
#include "llvm/IR/Constants.h"
2121
#include "llvm/IR/Dominators.h"
22+
#include "llvm/IR/IRBuilder.h"
2223
#include "llvm/IR/IntrinsicsAMDGPU.h"
2324
#include "llvm/InitializePasses.h"
2425
#include "llvm/Target/TargetMachine.h"
@@ -206,9 +207,12 @@ bool SIAnnotateControlFlow::openIf(BranchInst *Term) {
206207
if (isUniform(Term))
207208
return false;
208209

209-
Value *Ret = CallInst::Create(If, Term->getCondition(), "", Term);
210-
Term->setCondition(ExtractValueInst::Create(Ret, 0, "", Term));
211-
push(Term->getSuccessor(1), ExtractValueInst::Create(Ret, 1, "", Term));
210+
IRBuilder<> IRB(Term);
211+
Value *IfCall = IRB.CreateCall(If, {Term->getCondition()});
212+
Value *Cond = IRB.CreateExtractValue(IfCall, {0});
213+
Value *Mask = IRB.CreateExtractValue(IfCall, {1});
214+
Term->setCondition(Cond);
215+
push(Term->getSuccessor(1), Mask);
212216
return true;
213217
}
214218

@@ -217,15 +221,24 @@ bool SIAnnotateControlFlow::insertElse(BranchInst *Term) {
217221
if (isUniform(Term)) {
218222
return false;
219223
}
220-
Value *Ret = CallInst::Create(Else, popSaved(), "", Term);
221-
Term->setCondition(ExtractValueInst::Create(Ret, 0, "", Term));
222-
push(Term->getSuccessor(1), ExtractValueInst::Create(Ret, 1, "", Term));
224+
225+
IRBuilder<> IRB(Term);
226+
Value *ElseCall = IRB.CreateCall(Else, {popSaved()});
227+
Value *Cond = IRB.CreateExtractValue(ElseCall, {0});
228+
Value *Mask = IRB.CreateExtractValue(ElseCall, {1});
229+
Term->setCondition(Cond);
230+
push(Term->getSuccessor(1), Mask);
223231
return true;
224232
}
225233

226234
/// Recursively handle the condition leading to a loop
227235
Value *SIAnnotateControlFlow::handleLoopCondition(
228236
Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) {
237+
238+
auto CreateBreak = [this, Cond, Broken](Instruction *I) -> CallInst * {
239+
return IRBuilder<>(I).CreateCall(IfBreak, {Cond, Broken});
240+
};
241+
229242
if (Instruction *Inst = dyn_cast<Instruction>(Cond)) {
230243
BasicBlock *Parent = Inst->getParent();
231244
Instruction *Insert;
@@ -235,23 +248,20 @@ Value *SIAnnotateControlFlow::handleLoopCondition(
235248
Insert = L->getHeader()->getFirstNonPHIOrDbgOrLifetime();
236249
}
237250

238-
Value *Args[] = { Cond, Broken };
239-
return CallInst::Create(IfBreak, Args, "", Insert);
251+
return CreateBreak(Insert);
240252
}
241253

242254
// Insert IfBreak in the loop header TERM for constant COND other than true.
243255
if (isa<Constant>(Cond)) {
244256
Instruction *Insert = Cond == BoolTrue ?
245257
Term : L->getHeader()->getTerminator();
246258

247-
Value *Args[] = { Cond, Broken };
248-
return CallInst::Create(IfBreak, Args, "", Insert);
259+
return CreateBreak(Insert);
249260
}
250261

251262
if (isa<Argument>(Cond)) {
252263
Instruction *Insert = L->getHeader()->getFirstNonPHIOrDbgOrLifetime();
253-
Value *Args[] = { Cond, Broken };
254-
return CallInst::Create(IfBreak, Args, "", Insert);
264+
return CreateBreak(Insert);
255265
}
256266

257267
llvm_unreachable("Unhandled loop condition!");
@@ -287,7 +297,8 @@ bool SIAnnotateControlFlow::handleLoop(BranchInst *Term) {
287297
Broken->addIncoming(PHIValue, Pred);
288298
}
289299

290-
Term->setCondition(CallInst::Create(Loop, Arg, "", Term));
300+
CallInst *LoopCall = IRBuilder<>(Term).CreateCall(Loop, {Arg});
301+
Term->setCondition(LoopCall);
291302

292303
push(Term->getSuccessor(0), Arg);
293304

@@ -326,7 +337,7 @@ bool SIAnnotateControlFlow::closeControlFlow(BasicBlock *BB) {
326337
// Split edge to make Def dominate Use
327338
FirstInsertionPt = &*SplitEdge(DefBB, BB, DT, LI)->getFirstInsertionPt();
328339
}
329-
CallInst::Create(EndCf, Exec, "", FirstInsertionPt);
340+
IRBuilder<>(FirstInsertionPt).CreateCall(EndCf, {Exec});
330341
}
331342

332343
return true;

‎llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -6,25 +6,25 @@ define amdgpu_ps i32 @if_else(i32 %0) !dbg !5 {
66
; OPT-SAME: i32 [[TMP0:%.*]]) !dbg [[DBG5:![0-9]+]] {
77
; OPT-NEXT: [[C:%.*]] = icmp ne i32 [[TMP0]], 0, !dbg [[DBG13:![0-9]+]]
88
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i1 [[C]], metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13]]
9-
; OPT-NEXT: [[TMP2:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]])
10-
; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP2]], 0
11-
; OPT-NEXT: [[TMP4:%.*]] = extractvalue { i1, i64 } [[TMP2]], 1
12-
; OPT-NEXT: br i1 [[TMP3]], label [[FALSE:%.*]], label [[FLOW:%.*]], !dbg [[DBG14:![0-9]+]]
9+
; OPT-NEXT: [[TMP2:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]]), !dbg [[DBG14:![0-9]+]]
10+
; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP2]], 0, !dbg [[DBG14]]
11+
; OPT-NEXT: [[TMP4:%.*]] = extractvalue { i1, i64 } [[TMP2]], 1, !dbg [[DBG14]]
12+
; OPT-NEXT: br i1 [[TMP3]], label [[FALSE:%.*]], label [[FLOW:%.*]], !dbg [[DBG14]]
1313
; OPT: Flow:
1414
; OPT-NEXT: [[TMP5:%.*]] = phi i32 [ 33, [[FALSE]] ], [ undef, [[TMP1:%.*]] ]
15-
; OPT-NEXT: [[TMP6:%.*]] = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 [[TMP4]])
16-
; OPT-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP6]], 0
17-
; OPT-NEXT: [[TMP8:%.*]] = extractvalue { i1, i64 } [[TMP6]], 1
15+
; OPT-NEXT: [[TMP6:%.*]] = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 [[TMP4]]), !dbg [[DBG14]]
16+
; OPT-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP6]], 0, !dbg [[DBG14]]
17+
; OPT-NEXT: [[TMP8:%.*]] = extractvalue { i1, i64 } [[TMP6]], 1, !dbg [[DBG14]]
1818
; OPT-NEXT: br i1 [[TMP7]], label [[TRUE:%.*]], label [[EXIT:%.*]], !dbg [[DBG14]]
1919
; OPT: true:
2020
; OPT-NEXT: br label [[EXIT]], !dbg [[DBG15:![0-9]+]]
2121
; OPT: false:
2222
; OPT-NEXT: br label [[FLOW]], !dbg [[DBG16:![0-9]+]]
2323
; OPT: exit:
2424
; OPT-NEXT: [[RET:%.*]] = phi i32 [ [[TMP5]], [[FLOW]] ], [ 42, [[TRUE]] ], !dbg [[DBG17:![0-9]+]]
25-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]])
25+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]]), !dbg [[DBG18:![0-9]+]]
2626
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[RET]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
27-
; OPT-NEXT: ret i32 [[RET]], !dbg [[DBG18:![0-9]+]]
27+
; OPT-NEXT: ret i32 [[RET]], !dbg [[DBG18]]
2828
;
2929
%c = icmp eq i32 %0, 0, !dbg !13
3030
tail call void @llvm.dbg.value(metadata i1 %c, metadata !9, metadata !DIExpression()), !dbg !13
@@ -53,24 +53,24 @@ define amdgpu_ps void @loop_if_break(i32 %n) !dbg !19 {
5353
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[I]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25]]
5454
; OPT-NEXT: [[C:%.*]] = icmp ugt i32 [[I]], 0, !dbg [[DBG26:![0-9]+]]
5555
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i1 [[C]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26]]
56-
; OPT-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]])
57-
; OPT-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
58-
; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
59-
; OPT-NEXT: br i1 [[TMP1]], label [[LOOP_BODY:%.*]], label [[FLOW]], !dbg [[DBG27:![0-9]+]]
56+
; OPT-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]]), !dbg [[DBG27:![0-9]+]]
57+
; OPT-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0, !dbg [[DBG27]]
58+
; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1, !dbg [[DBG27]]
59+
; OPT-NEXT: br i1 [[TMP1]], label [[LOOP_BODY:%.*]], label [[FLOW]], !dbg [[DBG27]]
6060
; OPT: loop_body:
6161
; OPT-NEXT: [[I_NEXT:%.*]] = sub i32 [[I]], 1, !dbg [[DBG28:![0-9]+]]
6262
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[I_NEXT]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]]
6363
; OPT-NEXT: br label [[FLOW]], !dbg [[DBG29:![0-9]+]]
6464
; OPT: Flow:
6565
; OPT-NEXT: [[TMP3]] = phi i32 [ [[I_NEXT]], [[LOOP_BODY]] ], [ undef, [[LOOP]] ]
6666
; OPT-NEXT: [[TMP4:%.*]] = phi i1 [ false, [[LOOP_BODY]] ], [ true, [[LOOP]] ]
67-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
68-
; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]])
69-
; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]])
67+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]]), !dbg [[DBG27]]
68+
; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]]), !dbg [[DBG27]]
69+
; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]]), !dbg [[DBG27]]
7070
; OPT-NEXT: br i1 [[TMP6]], label [[EXIT:%.*]], label [[LOOP]], !dbg [[DBG27]]
7171
; OPT: exit:
72-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]])
73-
; OPT-NEXT: ret void, !dbg [[DBG30:![0-9]+]]
72+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]]), !dbg [[DBG30:![0-9]+]]
73+
; OPT-NEXT: ret void, !dbg [[DBG30]]
7474
;
7575
entry:
7676
br label %loop, !dbg !24

0 commit comments

Comments
 (0)