[Draft][RISCV] Give a simple testcase on RISCV regarding HwMode

Give a simple testcase on RISCV regarding HwMode as a reference.

Author: z30050559

llvm/lib/Target/RISCV/CMakeLists.txt

@@ -7,7 +7,7 @@ tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
 tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
+tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler --suppress-per-hwmode-duplicates=O1)
 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -640,6 +640,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   TRY_TO_DECODE_FEATURE(
       RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
       "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
+  TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureEncodingTmp),
+                           DecoderTable_EncodingTmp16, "For HwMode check");
   TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
                            "RISCV_C table (16-bit Instruction)");
 

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1150,15 +1150,21 @@ def Feature32Bit
     : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
 def Feature64Bit
     : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
+def FeatureEncodingTmp
+    : SubtargetFeature<"TmpE", "IsTmpE", "true", "Implements encoding tmp">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
              AssemblerPredicate<(all_of Feature64Bit),
                                 "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
              AssemblerPredicate<(all_of (not Feature64Bit)),
                                 "RV32I Base Instruction Set">;
+def IsTmpE : Predicate<"Subtarget->isETmp()">,
+             AssemblerPredicate<(all_of FeatureEncodingTmp),
+                                "RV32I Encoding tmp">;
 
 defvar RV32 = DefaultMode;
 def RV64           : HwMode<"+64bit", [IsRV64]>;
+def EncodingTmp    : HwMode<"+TmpE", [IsRV64]>;
 
 def FeatureRVE
     : SubtargetFeature<"e", "IsRVE", "true",

llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td

@@ -11,22 +11,60 @@
 //
 //===----------------------------------------------------------------------===//
 
+multiclass tmpEclass<bits<3> imm3> {
+def NAME#commonE : InstructionEncoding {
+  field bits<16> Inst;
+  field bits<16> SoftFail = 0;
+  let Size = 2;
+  bit mayLoad      = 0;
+  bit mayStore     = 0;
+  bit hasSideEffects = 0;
+  let Inst{1-0} = 0b01;
+  let Inst{6-2} = 0;
+  let Inst{7} = 0b1; //differ
+  let Inst{10-8} = imm3;
+  let Inst{12-11} = 0;
+  let Inst{15-13} = 0b011;
+}
+
+def NAME#specialE : InstructionEncoding {
+  field bits<16> Inst;
+  field bits<16> SoftFail = 0;
+  let Size = 2;
+  bit mayLoad      = 0;
+  bit mayStore     = 0;
+  bit hasSideEffects = 0;
+  let Inst{1-0} = 0b01;
+  let Inst{6-2} = 0;
+  let Inst{7} = 0b0; //differ
+  let Inst{10-8} = imm3;
+  let Inst{12-11} = 0;
+  let Inst{15-13} = 0b011;
+}
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class CMOPInst<bits<3> imm3, string opcodestr>
     : RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> {
   let Inst{6-2} = 0;
   let Inst{7} = 1;
   let Inst{10-8} = imm3;
   let Inst{12-11} = 0;
+  let EncodingInfos = EncodingByHwMode<[DefaultMode, EncodingTmp],
+                                       [!cast<InstructionEncoding>(NAME#commonE),
+                                        !cast<InstructionEncoding>(NAME#specialE)]>;
 }
 
 // CMOP1, CMOP5 is used by Zicfiss.
 let Predicates = [HasStdExtZcmop, NoHasStdExtZicfiss] in {
+  defm CMOP1 : tmpEclass<0>;
+  defm CMOP5 : tmpEclass<2>;
   def CMOP1 : CMOPInst<0, "cmop.1">, Sched<[]>;
   def CMOP5 : CMOPInst<2, "cmop.5">, Sched<[]>;
 }
 
 foreach n = [3, 7, 9, 11, 13, 15] in {
   let Predicates = [HasStdExtZcmop] in
+  defm CMOP # n : tmpEclass<!srl(n, 1)>;
   def CMOP # n : CMOPInst<!srl(n, 1), "cmop." # n>, Sched<[]>;
 }

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -60,7 +60,7 @@ def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
                    GenericTuneInfo;
 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
                                        NoSchedModel,
-                                       [Feature64Bit]>,
+                                       [Feature64Bit, FeatureEncodingTmp]>,
                    GenericTuneInfo;
 // Support generic for compatibility with other targets. The triple will be used
 // to change to the appropriate rv32/rv64 version.

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

@@ -100,11 +100,11 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
       RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
       FrameLowering(
           initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
-      InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
+      InstrInfo(*this), RegInfo(getHwMode(HwMode_RegInfo)), TLInfo(TM, *this) {
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
-  auto *RBI = new RISCVRegisterBankInfo(getHwMode());
+  auto *RBI = new RISCVRegisterBankInfo(getHwMode(HwMode_RegInfo));
   RegBankInfo.reset(RBI);
   InstSelector.reset(createRISCVInstructionSelector(
       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -165,6 +165,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   }
 
   bool is64Bit() const { return IsRV64; }
+  bool isETmp() const { return IsTmpE; }
   MVT getXLenVT() const {
     return is64Bit() ? MVT::i64 : MVT::i32;
   }

llvm/test/MC/RISCV/rvzcmop-valid.s

@@ -1,42 +1,50 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+zcmop -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+zcmop -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-64,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmop < %s \
-# RUN:     | llvm-objdump --mattr=+zcmop -d -r - \
+# RUN:     | llvm-objdump --triple=riscv32 --mattr=+zcmop -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmop < %s \
-# RUN:     | llvm-objdump --mattr=+zcmop -d -r - \
+# RUN:     | llvm-objdump --triple=riscv64 --mattr=+zcmop -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # CHECK-ASM-AND-OBJ: cmop.1
 # CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-ASM-64: encoding: [0x01,0x60]
 cmop.1
 
 # CHECK-ASM-AND-OBJ: cmop.3
 # CHECK-ASM: encoding: [0x81,0x61]
+# CHECK-ASM-64: encoding: [0x01,0x61]
 cmop.3
 
 # CHECK-ASM-AND-OBJ: cmop.5
 # CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-ASM-64: encoding: [0x01,0x62]
 cmop.5
 
 # CHECK-ASM-AND-OBJ: cmop.7
 # CHECK-ASM: encoding: [0x81,0x63]
+# CHECK-ASM-64: encoding: [0x01,0x63]
 cmop.7
 
 # CHECK-ASM-AND-OBJ: cmop.9
 # CHECK-ASM: encoding: [0x81,0x64]
+# CHECK-ASM-64: encoding: [0x01,0x64]
 cmop.9
 
 # CHECK-ASM-AND-OBJ: cmop.11
 # CHECK-ASM: encoding: [0x81,0x65]
+# CHECK-ASM-64: encoding: [0x01,0x65]
 cmop.11
 
 # CHECK-ASM-AND-OBJ: cmop.13
 # CHECK-ASM: encoding: [0x81,0x66]
+# CHECK-ASM-64: encoding: [0x01,0x66]
 cmop.13
 
 # CHECK-ASM-AND-OBJ: cmop.15
 # CHECK-ASM: encoding: [0x81,0x67]
+# CHECK-ASM-64: encoding: [0x01,0x67]
 cmop.15