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[PhaseOrdering] Add tests showing missed simplifications.
Add tests showing missed simplifications due to phase ordering.
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‎llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes='default<O3>' -S %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-macosx11.0.0"
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define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) {
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; CHECK-LABEL: define void @partial_unroll_forced(
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; CHECK-SAME: i32 [[N:%.*]], ptr nocapture readonly [[SRC:%.*]], ptr noalias nocapture writeonly [[DST:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 0
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; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.latch.preheader:
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; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64
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; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1
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; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]]
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; CHECK: loop.latch.preheader.new:
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; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 2147483646
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ]
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; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[LOOP_LATCH]] ]
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; CHECK-NEXT: [[SRC_IDX:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[L:%.*]] = load <8 x half>, ptr [[SRC_IDX]], align 16
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; CHECK-NEXT: [[DST_IDX:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[ADD:%.*]] = fadd <8 x half> [[L]], [[L]]
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; CHECK-NEXT: store <8 x half> [[ADD]], ptr [[DST_IDX]], align 16
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; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[SRC_IDX_1:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: [[L_1:%.*]] = load <8 x half>, ptr [[SRC_IDX_1]], align 16
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; CHECK-NEXT: [[DST_IDX_1:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: [[ADD_1:%.*]] = fadd <8 x half> [[L_1]], [[L_1]]
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; CHECK-NEXT: store <8 x half> [[ADD_1]], ptr [[DST_IDX_1]], align 16
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; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2
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; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
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; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
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; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA]], label [[LOOP_LATCH]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: exit.loopexit.unr-lcssa:
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; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[LOOP_LATCH]] ]
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; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0
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; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL:%.*]]
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; CHECK: loop.latch.epil:
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; CHECK-NEXT: [[SRC_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_UNR]]
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; CHECK-NEXT: [[L_EPIL:%.*]] = load <8 x half>, ptr [[SRC_IDX_EPIL]], align 16
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; CHECK-NEXT: [[DST_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[DST]], i64 [[INDVARS_IV_UNR]]
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; CHECK-NEXT: [[ADD_EPIL:%.*]] = fadd <8 x half> [[L_EPIL]], [[L_EPIL]]
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; CHECK-NEXT: store <8 x half> [[ADD_EPIL]], ptr [[DST_IDX_EPIL]], align 16
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%cmp14 = icmp slt i32 %iv, %N
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br i1 %cmp14, label %loop.latch, label %exit
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loop.latch:
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%iv.ext = zext i32 %iv to i64
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%src.idx = getelementptr <8 x half>, ptr %src, i64 %iv.ext
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%l = load <8 x half>, ptr %src.idx, align 16
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%dst.idx = getelementptr <8 x half>, ptr %dst, i64 %iv.ext
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%add = fadd <8 x half> %l, %l
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store <8 x half> %add, ptr %dst.idx, align 16
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%iv.next = add i32 %iv, 1
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br label %loop.header, !llvm.loop !0
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exit:
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ret void
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}
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!0 = distinct !{!0, !1, !2}
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!1 = !{!"llvm.loop.mustprogress"}
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!2 = !{!"llvm.loop.unroll.count", i32 2}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.mustprogress"}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"}
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;.

‎llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes='default<O3>' -S %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-macosx11.0.0"
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define i32 @read_only_loop_with_runtime_check(ptr noundef %array, i32 noundef %count, i32 noundef %n) {
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; CHECK-LABEL: define i32 @read_only_loop_with_runtime_check(
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; CHECK-SAME: ptr nocapture noundef readonly [[ARRAY:%.*]], i32 noundef [[COUNT:%.*]], i32 noundef [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP6_NOT:%.*]] = icmp eq i32 [[N]], 0
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; CHECK-NEXT: br i1 [[CMP6_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]]
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; CHECK: for.body.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[N]], -1
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; CHECK-NEXT: [[DOTNOT_NOT:%.*]] = icmp ult i32 [[TMP1]], [[COUNT]]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[IF_END:%.*]] ]
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; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]]
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; CHECK: for.body:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END]] ]
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; CHECK-NEXT: [[SUM_07:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[ADD]], [[IF_END]] ]
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; CHECK-NEXT: br i1 [[DOTNOT_NOT]], label [[IF_END]], label [[IF_THEN:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: tail call void @llvm.trap()
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; CHECK-NEXT: unreachable
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; CHECK: if.end:
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[ARRAY]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP2]], [[SUM_07]]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
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;
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entry:
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%array.addr = alloca ptr, align 8
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%count.addr = alloca i32, align 4
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%n.addr = alloca i32, align 4
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%sum = alloca i32, align 4
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%i = alloca i32, align 4
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store ptr %array, ptr %array.addr, align 8
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store i32 %count, ptr %count.addr, align 4
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store i32 %n, ptr %n.addr, align 4
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call void @llvm.lifetime.start.p0(i64 4, ptr %sum) #3
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store i32 0, ptr %sum, align 4
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call void @llvm.lifetime.start.p0(i64 4, ptr %i) #3
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store i32 0, ptr %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%0 = load i32, ptr %i, align 4
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%1 = load i32, ptr %n.addr, align 4
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%cmp = icmp ult i32 %0, %1
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond
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call void @llvm.lifetime.end.p0(i64 4, ptr %i) #3
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br label %for.end
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for.body: ; preds = %for.cond
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%2 = load i32, ptr %i, align 4
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%3 = load i32, ptr %count.addr, align 4
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%cmp1 = icmp uge i32 %2, %3
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %for.body
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call void @llvm.trap()
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%4 = load ptr, ptr %array.addr, align 8
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%5 = load i32, ptr %i, align 4
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%idxprom = zext i32 %5 to i64
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%arrayidx = getelementptr inbounds i32, ptr %4, i64 %idxprom
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%6 = load i32, ptr %arrayidx, align 4
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%7 = load i32, ptr %sum, align 4
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%add = add nsw i32 %7, %6
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store i32 %add, ptr %sum, align 4
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br label %for.inc
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for.inc: ; preds = %if.end
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%8 = load i32, ptr %i, align 4
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%inc = add i32 %8, 1
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store i32 %inc, ptr %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond.cleanup
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%9 = load i32, ptr %sum, align 4
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call void @llvm.lifetime.end.p0(i64 4, ptr %sum)
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ret i32 %9
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}
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declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
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declare void @llvm.trap()
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declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)

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