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Thorsten Schütt
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Revert "[GlobalIsel] Combine select of binops (#76763)"
This reverts commit 1687555.
1 parent 61bb3d4 commit a085402

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4 files changed

+28
-322
lines changed

4 files changed

+28
-322
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -910,9 +910,6 @@ class CombinerHelper {
910910

911911
bool tryFoldSelectOfConstants(GSelect *Select, BuildFnTy &MatchInfo);
912912

913-
/// Try to fold select(cc, binop(), binop()) -> binop(select(), X)
914-
bool tryFoldSelectOfBinOps(GSelect *Select, BuildFnTy &MatchInfo);
915-
916913
bool isOneOrOneSplat(Register Src, bool AllowUndefs);
917914
bool isZeroOrZeroSplat(Register Src, bool AllowUndefs);
918915
bool isConstantSplatVector(Register Src, int64_t SplatValue,

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 0 additions & 103 deletions
Original file line numberDiff line numberDiff line change
@@ -558,109 +558,6 @@ class GVecReduce : public GenericMachineInstr {
558558
}
559559
};
560560

561-
// Represents a binary operation, i.e, x = y op z.
562-
class GBinOp : public GenericMachineInstr {
563-
public:
564-
Register getLHSReg() const { return getReg(1); }
565-
Register getRHSReg() const { return getReg(2); }
566-
567-
static bool classof(const MachineInstr *MI) {
568-
switch (MI->getOpcode()) {
569-
// Integer.
570-
case TargetOpcode::G_ADD:
571-
case TargetOpcode::G_SUB:
572-
case TargetOpcode::G_MUL:
573-
case TargetOpcode::G_SDIV:
574-
case TargetOpcode::G_UDIV:
575-
case TargetOpcode::G_SREM:
576-
case TargetOpcode::G_UREM:
577-
case TargetOpcode::G_SMIN:
578-
case TargetOpcode::G_SMAX:
579-
case TargetOpcode::G_UMIN:
580-
case TargetOpcode::G_UMAX:
581-
// Floating point.
582-
case TargetOpcode::G_FMINNUM:
583-
case TargetOpcode::G_FMAXNUM:
584-
case TargetOpcode::G_FMINNUM_IEEE:
585-
case TargetOpcode::G_FMAXNUM_IEEE:
586-
case TargetOpcode::G_FMINIMUM:
587-
case TargetOpcode::G_FMAXIMUM:
588-
case TargetOpcode::G_FADD:
589-
case TargetOpcode::G_FSUB:
590-
case TargetOpcode::G_FMUL:
591-
case TargetOpcode::G_FDIV:
592-
case TargetOpcode::G_FPOW:
593-
// Logical.
594-
case TargetOpcode::G_AND:
595-
case TargetOpcode::G_OR:
596-
case TargetOpcode::G_XOR:
597-
return true;
598-
default:
599-
return false;
600-
}
601-
};
602-
};
603-
604-
// Represents an integer binary operation.
605-
class GIntBinOp : public GBinOp {
606-
public:
607-
static bool classof(const MachineInstr *MI) {
608-
switch (MI->getOpcode()) {
609-
case TargetOpcode::G_ADD:
610-
case TargetOpcode::G_SUB:
611-
case TargetOpcode::G_MUL:
612-
case TargetOpcode::G_SDIV:
613-
case TargetOpcode::G_UDIV:
614-
case TargetOpcode::G_SREM:
615-
case TargetOpcode::G_UREM:
616-
case TargetOpcode::G_SMIN:
617-
case TargetOpcode::G_SMAX:
618-
case TargetOpcode::G_UMIN:
619-
case TargetOpcode::G_UMAX:
620-
return true;
621-
default:
622-
return false;
623-
}
624-
};
625-
};
626-
627-
// Represents a floating point binary operation.
628-
class GFBinOp : public GBinOp {
629-
public:
630-
static bool classof(const MachineInstr *MI) {
631-
switch (MI->getOpcode()) {
632-
case TargetOpcode::G_FMINNUM:
633-
case TargetOpcode::G_FMAXNUM:
634-
case TargetOpcode::G_FMINNUM_IEEE:
635-
case TargetOpcode::G_FMAXNUM_IEEE:
636-
case TargetOpcode::G_FMINIMUM:
637-
case TargetOpcode::G_FMAXIMUM:
638-
case TargetOpcode::G_FADD:
639-
case TargetOpcode::G_FSUB:
640-
case TargetOpcode::G_FMUL:
641-
case TargetOpcode::G_FDIV:
642-
case TargetOpcode::G_FPOW:
643-
return true;
644-
default:
645-
return false;
646-
}
647-
};
648-
};
649-
650-
// Represents a logical binary operation.
651-
class GLogicalBinOp : public GBinOp {
652-
public:
653-
static bool classof(const MachineInstr *MI) {
654-
switch (MI->getOpcode()) {
655-
case TargetOpcode::G_AND:
656-
case TargetOpcode::G_OR:
657-
case TargetOpcode::G_XOR:
658-
return true;
659-
default:
660-
return false;
661-
}
662-
};
663-
};
664561

665562
} // namespace llvm
666563

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 28 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -6390,7 +6390,8 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
63906390
if (TrueValue.isZero() && FalseValue.isOne()) {
63916391
MatchInfo = [=](MachineIRBuilder &B) {
63926392
B.setInstrAndDebugLoc(*Select);
6393-
auto Inner = B.buildNot(CondTy, Cond);
6393+
Register Inner = MRI.createGenericVirtualRegister(CondTy);
6394+
B.buildNot(Inner, Cond);
63946395
B.buildZExtOrTrunc(Dest, Inner);
63956396
};
63966397
return true;
@@ -6400,7 +6401,8 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
64006401
if (TrueValue.isZero() && FalseValue.isAllOnes()) {
64016402
MatchInfo = [=](MachineIRBuilder &B) {
64026403
B.setInstrAndDebugLoc(*Select);
6403-
auto Inner = B.buildNot(CondTy, Cond);
6404+
Register Inner = MRI.createGenericVirtualRegister(CondTy);
6405+
B.buildNot(Inner, Cond);
64046406
B.buildSExtOrTrunc(Dest, Inner);
64056407
};
64066408
return true;
@@ -6410,7 +6412,8 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
64106412
if (TrueValue - 1 == FalseValue) {
64116413
MatchInfo = [=](MachineIRBuilder &B) {
64126414
B.setInstrAndDebugLoc(*Select);
6413-
auto Inner = B.buildZExtOrTrunc(TrueTy, Cond);
6415+
Register Inner = MRI.createGenericVirtualRegister(TrueTy);
6416+
B.buildZExtOrTrunc(Inner, Cond);
64146417
B.buildAdd(Dest, Inner, False);
64156418
};
64166419
return true;
@@ -6420,7 +6423,8 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
64206423
if (TrueValue + 1 == FalseValue) {
64216424
MatchInfo = [=](MachineIRBuilder &B) {
64226425
B.setInstrAndDebugLoc(*Select);
6423-
auto Inner = B.buildSExtOrTrunc(TrueTy, Cond);
6426+
Register Inner = MRI.createGenericVirtualRegister(TrueTy);
6427+
B.buildSExtOrTrunc(Inner, Cond);
64246428
B.buildAdd(Dest, Inner, False);
64256429
};
64266430
return true;
@@ -6430,7 +6434,8 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
64306434
if (TrueValue.isPowerOf2() && FalseValue.isZero()) {
64316435
MatchInfo = [=](MachineIRBuilder &B) {
64326436
B.setInstrAndDebugLoc(*Select);
6433-
auto Inner = B.buildZExtOrTrunc(TrueTy, Cond);
6437+
Register Inner = MRI.createGenericVirtualRegister(TrueTy);
6438+
B.buildZExtOrTrunc(Inner, Cond);
64346439
// The shift amount must be scalar.
64356440
LLT ShiftTy = TrueTy.isVector() ? TrueTy.getElementType() : TrueTy;
64366441
auto ShAmtC = B.buildConstant(ShiftTy, TrueValue.exactLogBase2());
@@ -6442,7 +6447,8 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
64426447
if (TrueValue.isAllOnes()) {
64436448
MatchInfo = [=](MachineIRBuilder &B) {
64446449
B.setInstrAndDebugLoc(*Select);
6445-
auto Inner = B.buildSExtOrTrunc(TrueTy, Cond);
6450+
Register Inner = MRI.createGenericVirtualRegister(TrueTy);
6451+
B.buildSExtOrTrunc(Inner, Cond);
64466452
B.buildOr(Dest, Inner, False, Flags);
64476453
};
64486454
return true;
@@ -6452,8 +6458,10 @@ bool CombinerHelper::tryFoldSelectOfConstants(GSelect *Select,
64526458
if (FalseValue.isAllOnes()) {
64536459
MatchInfo = [=](MachineIRBuilder &B) {
64546460
B.setInstrAndDebugLoc(*Select);
6455-
auto Not = B.buildNot(CondTy, Cond);
6456-
auto Inner = B.buildSExtOrTrunc(TrueTy, Not);
6461+
Register Not = MRI.createGenericVirtualRegister(CondTy);
6462+
B.buildNot(Not, Cond);
6463+
Register Inner = MRI.createGenericVirtualRegister(TrueTy);
6464+
B.buildSExtOrTrunc(Inner, Not);
64576465
B.buildOr(Dest, Inner, True, Flags);
64586466
};
64596467
return true;
@@ -6488,7 +6496,8 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
64886496
if ((Cond == True) || isOneOrOneSplat(True, /* AllowUndefs */ true)) {
64896497
MatchInfo = [=](MachineIRBuilder &B) {
64906498
B.setInstrAndDebugLoc(*Select);
6491-
auto Ext = B.buildZExtOrTrunc(TrueTy, Cond);
6499+
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
6500+
B.buildZExtOrTrunc(Ext, Cond);
64926501
B.buildOr(DstReg, Ext, False, Flags);
64936502
};
64946503
return true;
@@ -6499,7 +6508,8 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
64996508
if ((Cond == False) || isZeroOrZeroSplat(False, /* AllowUndefs */ true)) {
65006509
MatchInfo = [=](MachineIRBuilder &B) {
65016510
B.setInstrAndDebugLoc(*Select);
6502-
auto Ext = B.buildZExtOrTrunc(TrueTy, Cond);
6511+
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
6512+
B.buildZExtOrTrunc(Ext, Cond);
65036513
B.buildAnd(DstReg, Ext, True);
65046514
};
65056515
return true;
@@ -6510,9 +6520,11 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
65106520
MatchInfo = [=](MachineIRBuilder &B) {
65116521
B.setInstrAndDebugLoc(*Select);
65126522
// First the not.
6513-
auto Inner = B.buildNot(CondTy, Cond);
6523+
Register Inner = MRI.createGenericVirtualRegister(CondTy);
6524+
B.buildNot(Inner, Cond);
65146525
// Then an ext to match the destination register.
6515-
auto Ext = B.buildZExtOrTrunc(TrueTy, Inner);
6526+
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
6527+
B.buildZExtOrTrunc(Ext, Inner);
65166528
B.buildOr(DstReg, Ext, True, Flags);
65176529
};
65186530
return true;
@@ -6523,9 +6535,11 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
65236535
MatchInfo = [=](MachineIRBuilder &B) {
65246536
B.setInstrAndDebugLoc(*Select);
65256537
// First the not.
6526-
auto Inner = B.buildNot(CondTy, Cond);
6538+
Register Inner = MRI.createGenericVirtualRegister(CondTy);
6539+
B.buildNot(Inner, Cond);
65276540
// Then an ext to match the destination register.
6528-
auto Ext = B.buildZExtOrTrunc(TrueTy, Inner);
6541+
Register Ext = MRI.createGenericVirtualRegister(TrueTy);
6542+
B.buildZExtOrTrunc(Ext, Inner);
65296543
B.buildAnd(DstReg, Ext, False);
65306544
};
65316545
return true;
@@ -6534,54 +6548,6 @@ bool CombinerHelper::tryFoldBoolSelectToLogic(GSelect *Select,
65346548
return false;
65356549
}
65366550

6537-
bool CombinerHelper::tryFoldSelectOfBinOps(GSelect *Select,
6538-
BuildFnTy &MatchInfo) {
6539-
Register DstReg = Select->getReg(0);
6540-
Register Cond = Select->getCondReg();
6541-
Register False = Select->getFalseReg();
6542-
Register True = Select->getTrueReg();
6543-
LLT DstTy = MRI.getType(DstReg);
6544-
6545-
GBinOp *LHS = getOpcodeDef<GBinOp>(True, MRI);
6546-
GBinOp *RHS = getOpcodeDef<GBinOp>(False, MRI);
6547-
6548-
// We need two binops of the same kind on the true/false registers.
6549-
if (!LHS || !RHS || LHS->getOpcode() != RHS->getOpcode())
6550-
return false;
6551-
6552-
// Note that there are no constraints on CondTy.
6553-
unsigned Flags = (LHS->getFlags() & RHS->getFlags()) | Select->getFlags();
6554-
unsigned Opcode = LHS->getOpcode();
6555-
6556-
// Fold select(cond, binop(x, y), binop(z, y))
6557-
// --> binop(select(cond, x, z), y)
6558-
if (LHS->getRHSReg() == RHS->getRHSReg()) {
6559-
MatchInfo = [=](MachineIRBuilder &B) {
6560-
B.setInstrAndDebugLoc(*Select);
6561-
auto Sel = B.buildSelect(DstTy, Cond, LHS->getLHSReg(), RHS->getLHSReg(),
6562-
Select->getFlags());
6563-
B.buildInstr(Opcode, {DstReg}, {Sel, LHS->getRHSReg()}, Flags);
6564-
};
6565-
return true;
6566-
}
6567-
6568-
// Fold select(cond, binop(x, y), binop(x, z))
6569-
// --> binop(x, select(cond, y, z))
6570-
if (LHS->getLHSReg() == RHS->getLHSReg()) {
6571-
MatchInfo = [=](MachineIRBuilder &B) {
6572-
B.setInstrAndDebugLoc(*Select);
6573-
auto Sel = B.buildSelect(DstTy, Cond, LHS->getRHSReg(), RHS->getRHSReg(),
6574-
Select->getFlags());
6575-
B.buildInstr(Opcode, {DstReg}, {LHS->getLHSReg(), Sel}, Flags);
6576-
};
6577-
return true;
6578-
}
6579-
6580-
// FIXME: use isCommutable().
6581-
6582-
return false;
6583-
}
6584-
65856551
bool CombinerHelper::matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) {
65866552
GSelect *Select = cast<GSelect>(&MI);
65876553

@@ -6591,8 +6557,5 @@ bool CombinerHelper::matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) {
65916557
if (tryFoldBoolSelectToLogic(Select, MatchInfo))
65926558
return true;
65936559

6594-
if (tryFoldSelectOfBinOps(Select, MatchInfo))
6595-
return true;
6596-
65976560
return false;
65986561
}

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