[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention

This patch handles target lowering and calling convention.

For target lowering, the vector tuple type represented as multiple
scalable vectors is now changed to a single `MVT`, each `MVT` has a
corresponding register class.

The load/store of vector tuples are handled as the same way but need
another vector insert/extract instructions to get sub-register group.

Inline assembly constraint for vector tuple type can directly be modeled
as "vr" which is identical to normal vector registers.

For calling convention, it no longer needs an alternative algorithm to
handle register allocation, this makes the code easier to maintain and
read.

Author: 4vtomat

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -7283,17 +7283,19 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     EVT N1VT = N1.getValueType();
     assert(VT.isVector() && N1VT.isVector() &&
            "Extract subvector VTs must be vectors!");
-    assert(VT.getVectorElementType() == N1VT.getVectorElementType() &&
-           "Extract subvector VTs must have the same element type!");
-    assert((VT.isFixedLengthVector() || N1VT.isScalableVector()) &&
+    if (!N1VT.isRISCVVectorTuple())
+      assert(VT.getVectorElementType() == N1VT.getVectorElementType() &&
+             "Extract subvector VTs must have the same element type!");
+    assert((VT.isFixedLengthVector() || N1VT.isScalableVector() ||
+            N1VT.isRISCVVectorTuple()) &&
            "Cannot extract a scalable vector from a fixed length vector!");
     assert((VT.isScalableVector() != N1VT.isScalableVector() ||
             VT.getVectorMinNumElements() <= N1VT.getVectorMinNumElements()) &&
            "Extract subvector must be from larger vector to smaller vector!");
     assert(N2C && "Extract subvector index must be a constant");
     assert((VT.isScalableVector() != N1VT.isScalableVector() ||
-            (VT.getVectorMinNumElements() + N2C->getZExtValue()) <=
-                N1VT.getVectorMinNumElements()) &&
+            ((N1VT.isRISCVVectorTuple() ? 0 : VT.getVectorMinNumElements()) +
+             N2C->getZExtValue()) <= N1VT.getVectorMinNumElements()) &&
            "Extract subvector overflow!");
     assert(N2C->getAPIntValue().getBitWidth() ==
                TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
@@ -7516,18 +7518,23 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
            "Dest and insert subvector source types must match!");
     assert(VT.isVector() && N2VT.isVector() &&
            "Insert subvector VTs must be vectors!");
-    assert(VT.getVectorElementType() == N2VT.getVectorElementType() &&
-           "Insert subvector VTs must have the same element type!");
-    assert((VT.isScalableVector() || N2VT.isFixedLengthVector()) &&
-           "Cannot insert a scalable vector into a fixed length vector!");
+    if (!VT.isRISCVVectorTuple()) {
+      assert(VT.getVectorElementType() == N2VT.getVectorElementType() &&
+             "Insert subvector VTs must have the same element type!");
+      assert((VT.isScalableVector() || N2VT.isFixedLengthVector()) &&
+             "Cannot insert a scalable vector into a fixed length vector!");
+    }
+    if (VT.isRISCVVectorTuple())
+      assert((N2VT.isScalableVector() || N2VT.isRISCVVectorTuple()) &&
+             "Cannot insert a fixed length vector into a RISCV vector tuple!");
     assert((VT.isScalableVector() != N2VT.isScalableVector() ||
             VT.getVectorMinNumElements() >= N2VT.getVectorMinNumElements()) &&
            "Insert subvector must be from smaller vector to larger vector!");
     assert(isa<ConstantSDNode>(N3) &&
            "Insert subvector index must be constant");
     assert((VT.isScalableVector() != N2VT.isScalableVector() ||
-            (N2VT.getVectorMinNumElements() + N3->getAsZExtVal()) <=
-                VT.getVectorMinNumElements()) &&
+            ((VT.isRISCVVectorTuple() ? 0 : N2VT.getVectorMinNumElements()) +
+             N3->getAsZExtVal()) <= VT.getVectorMinNumElements()) &&
            "Insert subvector overflow!");
     assert(N3->getAsAPIntVal().getBitWidth() ==
                TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -3055,7 +3055,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
     return false;
 
   // TODO: For now we assume we know nothing about scalable vectors.
-  if (VT.isScalableVector())
+  if (VT.isScalableVector() || VT.isRISCVVectorTuple())
     return false;
 
   assert(VT.getVectorNumElements() == NumElts &&

llvm/lib/CodeGen/TargetLoweringBase.cpp

@@ -1382,6 +1382,10 @@ void TargetLoweringBase::computeRegisterProperties(
         // Try to widen the vector.
         for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
           MVT SVT = (MVT::SimpleValueType) nVT;
+          // Skip RISCV vector tuple types since they don't involve in any
+          // widen/narrow operation.
+          if (SVT.isRISCVVectorTuple())
+            continue;
           if (SVT.getVectorElementType() == EltVT &&
               SVT.isScalableVector() == IsScalable &&
               SVT.getVectorElementCount().getKnownMinValue() >

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1681,6 +1681,12 @@ MCRegister RISCVAsmParser::matchRegisterNameHelper(StringRef Name) const {
     Reg = MatchRegisterAltName(Name);
   if (isRVE() && Reg >= RISCV::X16 && Reg <= RISCV::X31)
     Reg = RISCV::NoRegister;
+
+  // Replace vector tuple with the starting register, e.g. V4M4_V8M4 -> V4
+  for (int i = 30; i >= 0; --i)
+    if (Name.starts_with("V" + utostr(i)))
+      return RISCV::V0 + i;
+
   return Reg;
 }